Xilinx LogiCORE IP Spartan-6 User Manual

18 www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010
Chapter 3: Running the Wizard
Generating the Core
This section provides instructions for generating an example GTP transceiver wrapper
core using the default values. The core and its supporting files, including the example
design, are generated in the project directory. For additional details about the example
design files and directories see
Implementing the Example Design, page 41.
1. Locate the Spartan-6 FPGA GTP Transceiver Wizard 1.8 in the taxonomy tree under:
/FPGA Features & Design/IO Interfaces. (See Figure 3-4)
2. Double-click Spartan-6 FPGA GTP Transceiver Wizard 1.8 to launch the Wizard.
X-Ref Target - Figure 3-4
Figure 3-4: Locating the GTP Transceiver Wizard

Xilinx LogiCORE IP Spartan-6 Specifications

General

Device Family	Spartan-6
Maximum Data Rate	3.2 Gbps
Number of Transceivers	Up to 8
Supported Protocols	Gigabit Ethernet
Power Supply	1.0V, 1.2V, 2.5V, 3.3V
Operating Temperature	Commercial, Industrial
Product Name	LogiCORE IP Spartan-6 FPGA Integrated Serial Transceivers