Xilinx Spartan 6 FPGA User Manual

10 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Each FPGA output pin or bidirectional I/O pin assumes its defined suspend mode
behavior, which is described as part of the FPGA design using a SUSPEND attribute.
The AWAKE pin goes Low, indicating that the FPGA is in suspend mode. The DONE pin
remains High while the FPGA is in suspend mode because the FPGA configuration data is
not lost.
This section details the waveform notes in Figure 1-2.
Entering Suspend in Figure 1-2
1. An external signal drives the FPGA's SUSPEND pin High, unconditionally forcing the
FPGA into the power-saving suspend mode (if SUSPEND_SYNC is not used). When
SUSPEND_SYNC is used, this phase does not complete until the SACK port of the
SUSPEND_SYNC primitive is asserted. Data values are captured for I/O pins with a
SUSPEND attribute set to DRIVE_LAST_VALUE; however, this value is not presented
until Step 4.
2. In response to the SUSPEND input going High or SACK assertion on the
SUSPEND_SYNC primitive, and after a delay of t
SUSPEND_GWE
, the FPGA write
protects and preserves the states of all clocked primitives. The states of all flip-flops,
block RAM, distributed RAM (LUT RAM), shift registers (SRL), and I/O latches are
preserved during suspend mode.
X-Ref Target - Figure 1-2
Figure 1-2: Suspend Mode Waveforms (Entering and Exiting)
ug394_c1_02_042910
Blocked
t
SUSPEND_DISABLE
t
AWAKE_GWE
t
AWAKE_GTS
SUSPEND Input
AWAKE Output
Flip-Flops, Block RAM,
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
Write Protected
Defined by SUSPEND Attribute
1
2
3
4
5
6
7
8
10
9
Entering Suspend Mode Exiting Suspend Mode
sw_gts_cycle
sw_gwe_cycle
t
SUSPEND_ENABLE
t
SUSPENDLOW_AWAKE
t
SUSPEND_GTS
t
SUSPENDHIGH_AWAKE
t
SUSPEND_GWE

Xilinx Spartan 6 FPGA Specifications

General

Brand	Xilinx
Model	Spartan 6 FPGA
Category	Microcontrollers
Language	English