VC707 Evaluation Board www.xilinx.com 17
UG885 (v1.4) May 12, 2014
Feature Descriptions
K15 DDR3_DM1 28 DM1
F12 DDR3_DM2 46 DM2
A14 DDR3_DM3 63 DM3
C23 DDR3_DM4 136 DM4
D25 DDR3_DM5 153 DM5
C31 DDR3_DM6 170 DM6
F31 DDR3_DM7 187 DM7
M16 DDR3_DQS0_N 10 DQS0_N
N16 DDR3_DQS0_P 12 DQS0_P
J12 DDR3_DQS1_N 27 DQS1_N
K12 DDR3_DQS1_P 29 DQS1_P
G16 DDR3_DQS2_N 45 DQS2_N
H16 DDR3_DQS2_P 47 DQS2_P
C14 DDR3_DQS3_N 62 DQS3_N
C15 DDR3_DQS3_P 64 DQS3_P
A27 DDR3_DQS4_N 135 DQS4_N
A26 DDR3_DQS4_P 137 DQS4_P
E25 DDR3_DQS5_N 152 DQS5_N
F25 DDR3_DQS5_P 154 DQS5_P
B29 DDR3_DQS6_N 169 DQS6_N
B28 DDR3_DQS6_P 171 DQS6_P
E28 DDR3_DQS7_N 186 DQS7_N
E27 DDR3_DQS7_P 188 DQS7_P
H20 DDR3_ODT0 116 ODT0
H18 DDR3_ODT1 120 ODT1
C29 DDR3_RESET_B 30 RESET_B
J17 DDR3_S0_B 114 S0_B
J20 DDR3_S1_B 121 S1_B
G17 DDR3_TEMP_EVENT 198 EVENT_B
F20 DDR3_WE_B 113 WE_B
K17 DDR3_CAS_B 115 CAS_B
E20 DDR3_RAS_B 110 RAS_B
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
FPGA (U1)
Pin
Net Name
J1 DDR3 Memory
Pin Number Pin Name