Xilinx VC707 - Page 78

78 www.xilinx.com VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
Chapter 1: VC707 Evaluation Board Features
over the 16-bit datapath from the Linear BPI Flash memory at a maximum synchronous
read rate of 80 MHz.
X-Ref Target - Figure 1-37
Figure 1-37: VC707 Board Configuration Circuit
UG885_c1_34_030512
RST_B
CLK
WE_B
OE_B
ADV_B
D[15:00]
A[26:01]
U3
P28F00AG18FE
1Gb Flash Memory
TCK
TMS
TDI
TDO
Bank 0
(VCCO = 1.8V)
CCLK
INIT_B
VBATT
M[2:0]
DONE
PROG_B
U1
FPGA
SW9
Bank 15
(VCCO = 1.8V)
Bank 14
(VCCO = 1.8V)
FWE_B
FOE_B
ADV_B
RS1
RS0
A[26:25]
A[23:16]
A[15:00]
D[15:00]
FCS_B
EMCCLK
GND
VCCAUXIO (2.0V)
5 kΩ
1.8V
261Ω
D6
BAS40-04
B1
GND
U40
Oscillator
80 MHz
Mode
Switch
CE_B
NC
Part of
SW11
GND
A27
NC
RDWR_B
WAIT
A25
A24
Q15
NDS331N
460 mW
GND
261Ω
DS10
GREEN
3.3V
1.8V
Part of
SW11
FLASH_A[25:0]
(VCC, VCCQ, 1.8V)
Send Feedback