Xilinx Virtex-6 FPGA Getting Started Guide

Virtex-6 FPGA Connectivity Kit Getting Started www.xilinx.com 35
UG664 (v1.4) July 6, 2011
Evaluating the Virtex-6 FPGA Connectivity TRD
c. Modify the Packet Size parameters for the XAUI Path and Raw Data Path transfers
(see Figure 26) and click Start test. Then view the payload statistics to review data
transfers on the XAUI Path and Raw Data Path channels of the DMA engine.
Note:
For packet sizes equal to 64 or 128 bytes, the throughput is reduced and might not be visible
on the Payload Statistics tab. The exact values can be viewed on the System Status tab.
X-Ref Target - Figure 26
Figure 26: Packet Size Field in the Payload Statistics Tab
UG664_14_091010

Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English