Xilinx Virtex-6 FPGA

Virtex-6 FPGA Connectivity Kit Getting Started www.xilinx.com 61
UG664 (v1.4) July 6, 2011
Next Steps
XAUI
Figure 58 shows the XAUI design module. Figure 59 shows the design file structure.
X-Ref Target - Figure 58
Figure 58: XAUI Design Module
X-Ref Target - Figure 59
Figure 59: XAUI Design FIles
UG664_22_060110
XAUI
GTX Transceivers
Control
Data
Control
Data
64
@156.25 MHz
UG664_23_090810
v6_pcie_10Gdma_ddr3_xaui_axi
design
ip_cores
xaui