Xilinx Virtex-6 FPGA Getting Started Guide

Virtex-6 FPGA Connectivity Kit Getting Started www.xilinx.com UG664 (v1.4) July 6, 2011
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Revision History
The following table shows the revision history for this document.
Date Version Revision
02/26/10 1.0 Initial Xilinx release.
06/11/10 1.1 Removed references to specific release numbers for the ISE Design Suite, where
applicable. Replaced Figure 1, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, and
Figure 27.
Removed update DVD from Connectivity Kit Contents. Added “in loopback mode” to
step b, page 31. Removed DDR3 from Raw Data Path bullet in step 2a on page 33. In
step 2b on page 33, changed the minimum value of the range from 128 to 64 for the XAUI
and Raw Data paths and changed the Raw Data path option to one Packet Size instead
of a minimum and a maximum. In step 2c on page 35, indicated to click Start test.
Added the note under Figure 26. Replaced the “ISE 11.1 Software Installation” and
“ISE 11.4 Software Update Installation” sections with a link to the Installation, Licensing,
and Release Notes document. In step 8, page 40, removed the ISE Design Suite release
number from the path. In Modifying the Virtex-6 FPGA Targeted Reference Design,
added the note on page 42. Changed the command in step 4c on page 42. Changed the
names of the BIT and MCS files in step 5d on page 43. Removed “double-click” from the
Windows based script in step 8c on page 44. Removed sentence about the command
shell opening from step 8d on page 44. Added the Next Steps section.
08/10/10 1.2 In step 4c on page 42, changed the filename to mig3_5.xco from mig3_4.xco. In
Table 2, changed the implementation software tool entry to ISE Design Suite.
10/05/10 1.3 Added information for AXI4 protocol.
07/06/11 1.4 Removed descriptions of Virtex-6 FPGA Connectivity TRD being available in non-AXI4
protocol version throughout. Replaced v6_trd_quickstart with v6_trd_lin_quickstart.
Added Windows platform to Board and Connectivity Targeted Reference Design
Features. Updated step 6c on page 14
. Added Install Windows Driver. Updated
Figure 21. Added Install Linux Driver heading before step 12 on page 27.

Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English