Xilinx Virtex-6 FPGA

32 www.xilinx.com Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Getting Started with the Connectivity Targeted Reference Design Demo
18. Performance Monitor Application: In the dialog box shown in Figure 24, verify data
throughput and error-free operation:
a. Verify the PCIe throughput is approximately 10 Gbps.
b. Verify the DMA channel throughput for the XAUI path and DMA channel
throughput for the Raw Data path together is approximately 9 Gbps.
c. Verify there are no buffer descriptor errors for error-free operation.
Congratulations! The Virtex-6 FPGA Connectivity Kit is now set up. The pre-built
connectivity targeted reference design demonstration has been tested, using the built-in
block for PCI Express (4-lane 5 GT/s configuration for PCI Express, v2.0), XAUI
LogiCORE IP module, a Virtual FIFO memory controller that interfaces to the onboard
DDR3 SODIMM device, and a third-party DMA controller for PCI Express.
X-Ref Target - Figure 24
Figure 24: Verify Error-Free Operation in the Performance Monitor
UG664_10_090810