Xilinx Virtex-6 FPGA

30 www.xilinx.com Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Getting Started with the Connectivity Targeted Reference Design Demo
16. Performance Monitor Application: Verify the board status.
a. Click on the System Status tab to verify the status of the ML605 board and the
PCIe link (see Figure 22):
- Link Status: Up
This confirms that the PCIe link is up and a PCIe connection is established
between the Virtex-6 FPGA Endpoint for PCI Express and the PC
motherboard chipset.
- Link Speed: 5.0 Gbps
This confirms that the PCIe link is operating at line rate speeds per PCI
Express, v2.0.
- Link Width: x4
This confirms that the PCIe link is trained as a x4 link.
X-Ref Target - Figure 22
Figure 22: Verify Board Status in the Performance Monitor
UG664_08_090810