Xilinx Virtex-7 VC7203 User Manual

58 www.xilinx.com VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
Appendix C: Master Constraints File Listing
set_property PACKAGE_PIN D36 [get_ports FMC2_LA18_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA18_CC_N]
set_property PACKAGE_PIN B36 [get_ports FMC2_LA19_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA19_P]
set_property PACKAGE_PIN A37 [get_ports FMC2_LA19_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA19_N]
set_property PACKAGE_PIN B34 [get_ports FMC2_LA20_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA20_P]
set_property PACKAGE_PIN A34 [get_ports FMC2_LA20_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA20_N]
set_property PACKAGE_PIN B39 [get_ports FMC2_LA21_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA21_P]
set_property PACKAGE_PIN A39 [get_ports FMC2_LA21_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA21_N]
set_property PACKAGE_PIN A35 [get_ports FMC2_LA22_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA22_P]
set_property PACKAGE_PIN A36 [get_ports FMC2_LA22_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA22_N]
set_property PACKAGE_PIN C38 [get_ports FMC2_LA23_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA23_P]
set_property PACKAGE_PIN C39 [get_ports FMC2_LA23_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA23_N]
set_property PACKAGE_PIN B37 [get_ports FMC2_LA24_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA24_P]
set_property PACKAGE_PIN B38 [get_ports FMC2_LA24_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA24_N]
set_property PACKAGE_PIN E32 [get_ports FMC2_LA25_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA25_P]
set_property PACKAGE_PIN D32 [get_ports FMC2_LA25_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA25_N]
set_property PACKAGE_PIN B32 [get_ports FMC2_LA26_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA26_P]
set_property PACKAGE_PIN B33 [get_ports FMC2_LA26_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA26_N]
set_property PACKAGE_PIN E33 [get_ports FMC2_LA27_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA27_P]
set_property PACKAGE_PIN D33 [get_ports FMC2_LA27_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA27_N]
set_property PACKAGE_PIN C33 [get_ports FMC2_LA28_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA28_P]
set_property PACKAGE_PIN C34 [get_ports FMC2_LA28_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA28_N]
set_property PACKAGE_PIN G32 [get_ports FMC2_LA29_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA29_P]
set_property PACKAGE_PIN F32 [get_ports FMC2_LA29_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA29_N]
set_property PACKAGE_PIN F36 [get_ports FMC2_LA30_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA30_P]
set_property PACKAGE_PIN F37 [get_ports FMC2_LA30_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA30_N]
set_property PACKAGE_PIN F34 [get_ports FMC2_LA31_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA31_P]
set_property PACKAGE_PIN F35 [get_ports FMC2_LA31_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA31_N]
set_property PACKAGE_PIN H33 [get_ports FMC2_LA32_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA32_P]
set_property PACKAGE_PIN G33 [get_ports FMC2_LA32_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA32_N]
set_property PACKAGE_PIN E37 [get_ports FMC2_LA33_P]
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Xilinx Virtex-7 VC7203 Specifications

General

FPGA Family	Virtex-7
Transceiver	GTH
GTH Transceivers	16
Maximum Data Rate	13.1 Gbps
Transceivers	16
Maximum Transceiver Speed	13.1 Gbps
Maximum User I/O	600
Process Technology	28nm
Block RAM	38 Mb
Power Supply Voltage	0.9V
Operating Temperature Range	Industrial