Xilinx Virtex-7 VC7203 User Manual

VC7203 GTX Transceiver Characterization Board www.xilinx.com 29
UG957 (v1.3) October 17, 2014
Detailed Description
USB-to-UART Bridge
Callout 21, Figure 1-2.
A USB-to-UART bridge (U34, Silicon Laboratories CP2103) is provided for serial
communication between a host computer and the FPGA over a USB cable. The USB
connector on the board is a mini-B receptacle (J79) and its pinout is shown in Table 1-15.
The CP2103 supports an I/O voltage range of 1.8V to 3.3V. Xilinx UART IP is expected to
be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using
four signal pins:
•Transmit (TX)
• Receive (RX)
• Request to Send (RTS)
• Clear to Send (CTS)
Connections of these signals between the FPGA and the CP2103 are listed in Table 1-16.
A10 119_REFCLK0_P 119 J163
A9 119_REFCLK0_N 119 J163
C10 119_REFCLK1_P 119 J163
C9 119_REFCLK1_N 119 J163
Table 1-14: GTX Transceiver Reference Clock Inputs (Cont’d)
U1 FPGA Pin Net Name Quad Connector
Table 1-15: USB Mini-B Receptacle Pin Assignments and Signals
J79 Pin Signal Name Description
1VBUS
+5V into the CP2103 USB-to-UART bridge at U34.
Used to sense USB network connection.
2 USB_DATA_N Bidirectional differential serial data (N-side).
3 USB_DATA_P Bidirectional differential serial data (P-side).
4 GROUND Signal ground.
Table 1-16: FPGA to UART Connections
FPGA (U1)
Schematic Net
Name
Device (U34)
Pin Function Direction I/O Standard Pin Function Direction
B31 RTS Output LVCMOS18 USB_CTS_I_B 22 CTS Input
C31 CTS Input LVCMOS18 USB_RTS_0_B 23 RTS Output
A30 TX Output LVCMOS18 USB_RXD_I 24 RXD Input
A29 RX Input LVCMOS18 USB_TXD_0 25 TXD Output
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Xilinx Virtex-7 VC7203 Specifications

General

FPGA Family	Virtex-7
Transceiver	GTH
GTH Transceivers	16
Maximum Data Rate	13.1 Gbps
Transceivers	16
Maximum Transceiver Speed	13.1 Gbps
Maximum User I/O	600
Process Technology	28nm
Block RAM	38 Mb
Power Supply Voltage	0.9V
Operating Temperature Range	Industrial