Xilinx Virtex-7 VC7203 User Manual

18 www.xilinx.com VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
Chapter 1: VC7203 Board Features and Operation
The switch settings for selecting each address are shown in Table 1-6.
200 MHz 2.5V LVDS Oscillator
U35 (callout 11, Figure 1-2).
The VC7203 board has one 200 MHz 2.5V LVDS oscillator (U35) connected to multi-region
clock capable (MRCC) inputs on the FPGA. Table 1-7 lists the FPGA pin connections to the
LVDS oscillator.
Differential SMA MRCC Pin Inputs
Callout 30, Figure 1-2.
The VC7203 board provides two pairs of differential SMA transceiver clock inputs that can
be used for connecting to an external function generator. The FPGA MRCC pins are
connected to the SMA connectors as shown in Table 1-8.
Table 1-6: SW8 DIP Switch Configuration
Configuration Bitstream Address ADR2 ADR1 ADR0
0 ONONON
1ONONOFF
2ONOFFON
3ONOFFOFF
4OFFONON
5OFFONOFF
6OFFOFFON
7OFFOFFOFF
Table 1-7: LVDS Oscillator MRCC Connections
FPGA (U1)
Schematic
Net Name
Device (U35)
Pin Function Direction I/O Standard Pin Function Direction
E19 SYSTEM CLOCK_P Input LVDS LVDS_OSC_P 4 200 MHz LVDS oscillator Output
E18 SYSTEM CLOCK_N Input LVDS LVDS_OSC_N 5 201 MHz LVDS oscillator Output
Table 1-8: Differential SMA Clock Connections
FPGA (U1)
Schematic Net Name SMA Connector
Pin Function Direction I/O Standard
H19 USER CLOCK_1_P Input LVDS_25 CLK_DIFF_1_P J99
G18 USER CLOCK_1_N Input LVDS_25 CLK_DIFF_1_N J100
K39 USER CLOCK_2_P Input LVDS_25 CLK_DIFF_2_P J98
K40 USER CLOCK_2_N Input LVDS_25 CLK_DIFF_2_N J101
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Xilinx Virtex-7 VC7203 Specifications

General

FPGA Family	Virtex-7
Transceiver	GTH
GTH Transceivers	16
Maximum Data Rate	13.1 Gbps
Transceivers	16
Maximum Transceiver Speed	13.1 Gbps
Maximum User I/O	600
Process Technology	28nm
Block RAM	38 Mb
Power Supply Voltage	0.9V
Operating Temperature Range	Industrial