44 www.xilinx.com VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
Chapter 1: VC7203 Board Features and Operation
XADC
Callout 31, Figure 1-2.
7 series FPGAs provide an Analog Front End (XADC) block. The XADC block includes a
dual 12-bit, 1 MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors. See 7 Series
FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital
Converter User Guide (UG480)
[Ref 1] for details on the capabilities of the analog front end.
The VC7203 board provides two options for providing power (VCCADC) to the analog
circuitry in the XADC. Either option can be selected by placing a shunt in one of two
positions on the 3-pin VCCADC SELECT header, J141 (callout 31, Figure 1-2):
• Pins 1-2 (VCCAUX): In this configuration VCCADC is provided from VCCAUX
through a low pass filter network.
• Pin 2-3 (REG): In this configuration VCCADC is provided by an onboard regulator,
U43 (Analog Devices P/N ADP123AUJZ-R7). The output voltage of the regulator
VCCADC can be adjusted using the potentiometer R233.
In addition, the VC7203 board provides two options for providing the reference voltage for
the analog-to-digital converter. Either option can be selected by placing a shunt in one of
two positions on the 3-pin VREF SEL header J142 (callout 31, Figure 1-2):
• Pins 1-2 (REG): In this configuration the ADC reference voltage is provided by an
onboard, low-temperature coefficient 1.25V reference, U45 (Texas Instruments P/N
REF3012AIDBZT)
• Pin 2-3 (AGND): In this configuration the VREFP on XADC is connected to analog
ground and the ADC uses an on-chip reference.
AR17 FMC3_LA28_N H32
AU19 FMC3_LA29_P G30
AV19 FMC3_LA29_N G31
AT20 FMC3_LA30_P H34
AT19 FMC3_LA30_N H35
AV16 FMC3_LA31_P G33
AW16 FMC3_LA31_N G34
AT16 FMC3_LA32_P H37
AU16 FMC3_LA32_N H38
BB19 FMC3_LA33_P G36
BB18 FMC3_LA33_N G37
AR20 FMC3_PRSNT_M2C_L H2
Table 1-20: VITA 57.1 FMC1 HPC Connections at JA4 (Cont’d)
U1 FPGA Pin Net Name FMC Pin
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