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ZC
U104 Boar
d User Guide
59
UG1267 (v1.1) Oct
ober 9, 2018
www
.xilinx.com
Chapter 3:
Boar
d Component De
scriptions
X-Ref Targ
et - Figure 3-17
Figure 3-17:
HDMI TX Interf
ace Circuit
X16535-0201
18
X-Ref Targ
et - Figure 3-18
Figure 3-18:
HDMI RX Interf
ace Circuit
X20258-020218
S
e
n
d
F
e
e
d
b
a
c
k
58
60
Table of Contents
Main Page
Default Chapter
2
Revision History
2
Table of Contents
3
Chapter 1: Introduction
5
Overview
5
Additional Resources
5
Block Diagram
6
Board Features
7
Board Specifications
9
Dimensions
9
Environmental
9
Operating Voltage
10
Chapter 2: Board Setup and Configuration
11
Board Component Location
11
Electrostatic Discharge Caution
11
Default Jumper and Switch Settings
15
Jumpers
15
Switches
16
Mpsoc Device Configuration
16
Jtag
16
Quad SPI
17
Chapter 3: Board Component Descriptions
18
Overview
18
Component Descriptions
18
Zynq Ultrascale+ XCZU7EV Mpsoc
18
Encryption Key Battery Backup Circuit
22
PS-Side: DDR4 Component Memory
24
PL-Side: DDR4 SODIMM Socket
29
Psmio
33
Quad SPI Flash Memory (MIO 0-5)
34
USB 3.0 Transceiver and USB 2.0 ULPI PHY
35
SD Card Interface
37
Programmable Logic JTAG Programming Options
39
PS M.2 SATA Connector
39
Clock Generation
44
IDT8T49N287 Femtoclock NG Octal Universal Frequency Translator
45
GEM3 Ethernet (MIO 64-77)
46
10/100/1000 Mhz Tri-Speed Ethernet PHY
46
I2C1 (Mio 16-17)
50
FT4232HL USB UART Interface (MIO 18-21)
52
Uart0 (Mio 18-19)
53
Uart1 (Mio 20-21)
54
Can1 (Mio 24-25)
54
Dpaux (Mio 27-30)
55
HDMI Video Output
57
HDMI Clock Recovery
61
User PMOD GPIO Connectors
62
User I2C1 Receptacle
64
User I/O
64
Power and Status Leds
68
GTH Transceivers
70
PS-Side: GTR Transceivers
74
FPGA Mezzanine Card Interface
76
FMC LPC Connector J5
76
Cooling Fan Connector
79
Switches
80
Board Power System
83
Monitoring Voltage and Current
85
Appendix A: VITA 57.1 FMC Connector Pinouts
86
Overview
86
Appendix B: Xilinx Constraints File
87
Overview
87
Appendix C: Regulatory and Compliance Information
88
Overview
88
CE Directives
88
CE Standards
88
Electromagnetic Compatibility
88
Safety
89
Markings
89
Appendix D: Additional Resources and Legal Notices
90
Xilinx Resources
90
Solution Centers
90
Documentation Navigator and Design Hubs
90
References
91
Please Read: Important Legal Notices
92
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