Xilinx ZCU104 User Manual

ZCU104 Board User Guide 72
UG1267 (v1.1) October 9, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
FMC LPC
The FMC low pin count (LPC) connector J5 has its full LA[00:33] bus connected across the
XCZU7EV MPSoC PL banks 67 and 68.
The three FMC LPC clocks are connected as follows:
• FMC_LPC_GBTCLK0_M2C_C_P/N is connected to GTH bank 226 MGTREFCLK0
• FMC_LPC_CLK0_M2C_P/N is connected to PL bank 67 (LA[00:16]) GC pins E15/E14
• FMC_LPC_CLK1_M2C_P/N is connected to PL bank 68 (LA[17:33]) GC pins G10/F10
HDMI
Three PL-side GTH transceivers are dedicated for HDMI source and sink. Modes supported
are 4K, 2K at 60 f/s, and 2160p60. External circuitry for interfacing TMDS signals with the
GTH transceivers is required. Table 3-26 and Table 3-27 list MGTH banks 226 and 227
connections, respectively.
Table 3-26: GTH Bank 226 Interface Connections
XCZU7EV
(U1) Pin
XCZU7EV Pin
Name
Schematic Net Name
(2)
Connected To
Pin No. Pin Name Device
U6 MGTHTXP0 Not connected NA NA
NA
U5 MGTHTXN0 Not connected NA NA
V4 MGTHRXP0 Not connected NA NA
V3 MGTHRXN0 Not connected NA NA
T4 MGTHTXP1 Not connected NA NA
T3 MGTHTXN1 Not connected NA NA
U2 MGTHRXP1 Not connected NA NA
U1 MGTHRXN1 Not connected NA NA
R6 MGTHTXP2 Not connected NA NA
R5 MGTHTXN2 Not connected NA NA
R2 MGTHRXP2 Not connected NA NA
R1 MGTHRXN2 Not connected NA NA
N6 MGTHTXP3 Not Connected NA NA
NA
N5 MGTHTXN3 Not Connected NA NA
P4 MGTHRXP3 Not Connected NA NA
P3 MGTHRXN3 Not Connected NA NA
V8 MGTREFCLK0P FMC_LPC_GBTCLK0_M2C_C_P
(1)
D4 GBTCLK0_M2C_P
FMC LPC J5
V7 MGTREFCLK0N FMC_LPC_GBTCLK0_M2C_C_N
(1)
D5 GBTCLK0_M2C_N
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Xilinx ZCU104 Specifications

General

Brand	Xilinx
Model	ZCU104
Category	Motherboard
Language	English