Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 39
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 3: APU Software Platform
Stream Out
The Stream Out panel allows you to configure streaming parameters. See Figure 3-13 and
Tab le 3 -5 .
Note:
IDR is not user configurable. In the encoder code, the idr value = gop-length.
X-Ref Target - Figure 3-13
Figure 3-13: Stream Out Panel
Table 3-5: Stream Out Panel Settings
Parameter Setting
SINK Provides the sink option for the stream out case. It is set to PS Ethernet.
Host IP Provides the option to enter the Host IP address.
IP Shows the IP address of the board if the Ethernet link is up. If no Ethernet link is
connected, it shows Not Connected.
Port Port number of the Ethernet link. The default is 5004.
X19921-112718
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Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C