RFSoC Data Converter Evaluation Tool User Guide 25
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 3: Hardware Design
DAC0 Loopback select 3 Reserved 35 Reserved 67
DAC1 Memory Loopback Reset 4 ADC0203 FIFO Reset 36 DAC Multi Tile Select 68
DAC1 Loopback select 5 ADC0203_IQ_Merge_sel 37 Reserved 69
DAC1 Channel Control 6 ADC0203 Channel Control 38 Reserved 70
DAC2 Loopback select 7 Reserved 39 Reserved 79:71
DAC2 Memory Loopback Reset 8 ADC1011 FIFO Reset 40 ADC Channel Mux
select
82:80
DAC3 Loopback select 9 ADC1011_IQ_Merge_sel 41 Reserved 83
DAC2 Channel Control 10 ADC1011 Channel Control 42 ADC Multi Tile Select 84
DAC4 Loopback select 11 Reserved 43 ADC Fabric Filter
Select
90
DAC3 Memory Loopback Reset 12 ADC1213 FIFO Reset 44 DAC Fabric Filter
Select
91
DAC5 Loopback select 13 ADC1213_IQ_Merge_sel 45
DAC3 Channel Control 14 ADC1213 Channel Control 46
DAC6 Loopback select 15 Reserved 47
DAC4 Memory Loopback Reset 16 ADC2021 FIFO Reset 48
DAC7 Loopback select 17 ADC2021_IQ_Merge_sel 49
DAC4 Channel Control 18 ADC2021 Channel Control 50
Reserved 19 Reserved 51
DAC5 Memory Loopback Reset 20 ADC2223 FIFO Reset 52
Reserved 21 ADC2223_IQ_Merge_sel 53
DAC5 Channel Control 22 ADC2223 Channel Control 54
Reserved 23 Reserved 55
DAC6 Memory Loopback Reset 24 ADC3031 FIFO Reset 56
Reserved 25 ADC3031_IQ_Merge_sel 57
DAC6 Channel Control 26 ADC3031 Channel Control 58
Reserved 27 Reserved 59
DAC7 Memory Loopback Reset 28 ADC3132 FIFO Reset 60
Reserved 29 ADC3132_IQ_Merge_sel 61
DAC7 Channel Control 30 ADC3132 Channel Control 62
Reserved 31 Reserved 63
Table 3-2: Control Signals (Cont’d)
DAC ADC Common
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