Zynq UltraScale+ User Manual

RFSoC Data Converter Evaluation Tool User Guide 35
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 4: Clocking
DAC 4 block- output AXIS data FIFOs x (dac reset_4_n)
DAC 5 block- output AXIS data FIFOs x (dac reset_5_n)
DAC 6 block- output AXIS data FIFOs x (dac reset_6_n)
DAC 7 block- output AXIS data FIFOs x (dac reset_7_n)
Table 4-3: Reset Distribution in the Evaluation Tool Design (Cont’d)
Logic Block pl_resetn0 ddr4_sync_rst
User-controlled
Reset Block
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Zynq UltraScale+ Specifications

General

Max Transceivers	Up to 32
Transceiver Speed	Up to 32.75 Gbps
Family	Zynq UltraScale+
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
Max Memory	DDR4
Power Consumption	Varies by configuration, typically 10W to 30W
Operating Temperature	Industrial (-40°C to +100°C), Extended (-40°C to +125°C)
Package Options	Various BGA packages
Category	FPGA SoC