Zynq UltraScale+ User Manual

RFSoC Data Converter Evaluation Tool User Guide 67
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Appendix A: Reference Design Protocol Specification
°
This function should be pointed to the method used to actually transmit strings or
characters over the desired communication interface.
• Non-blocking
°
Implementation of command and datapath is non-blocking.
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Zynq UltraScale+ Specifications

General

Max Transceivers	Up to 32
Transceiver Speed	Up to 32.75 Gbps
Family	Zynq UltraScale+
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
Max Memory	DDR4
Power Consumption	Varies by configuration, typically 10W to 30W
Operating Temperature	Industrial (-40°C to +100°C), Extended (-40°C to +125°C)
Package Options	Various BGA packages
Category	FPGA SoC