DeltaIA
DeltaVA
DeltaIB
DeltaVB
DeltaIC
DeltaVC
PU_DI_A
PU_DI_B
PU_DI_C
PU_DI
PU_DV
PU_DV_A
PU_DV_B
PU_DV_B
ANSI12000165-2-en.vsd
intBlock
AND
AND
AND
AND
AND
AND
AND
OROR
AND
OR
20 ms
0
20 ms
0
20 ms
0
20 ms
0
20 ms
0
20 ms
0
ANSI12000165 V2 EN-US
Figure 393: Internal signals DeltaV or DeltaI and the corresponding output signals
13.2.7.3 Dead line detection
M13679-44 v4
A simplified diagram for the functionality is found in figure 394. A dead phase condition is
indicated if both the voltage and the current in one phase is below their respective setting values
VDLDPU
and
IDLDPU
. If at least one phase is considered to be dead the output DLD1PH and the
internal signal DeadLineDet1Ph is activated. If all three phases are considered to be dead the
output DLD3PH is activated
Section 13 1MRK 502 066-UUS B
Secondary system supervision
738
Technical manual
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