102
Chapter 5 Theory of Operation
Digital Waveform, Pulse, and Sync
5
LE and TE are outputs from register U1504 which is clocked
differentially by WFDAC_CLK±. The pulse period always consists of an
integral number of clocks; the clock frequency is controlled to achieve
fine period resolution. The pulse itself consists of a number of clocks plus
the delay provided by the delay circuit; fine control of the pulse width is
achieved by varying the delay via a control voltage, V_TEDLY.
Before the TE pulse, U1505-A holds integrating capacitor C1511 at an
ECL high logic level (approximately –0.8 V). When the TE pulse occur,
the flip-flop’s output goes low, but being an open-emitter output,
it cannot sink current from the capacitor. Instead, the capacitor begins
charging in a negative direction through R1549. U1506-A compares the
voltage on C1511 to a threshold determined by V_TEDLY. When the
capacitor’s voltage crosses the threshold, the comparator’s inverting
output goes high and sets U1505-A back to its original state. This rapidly
charges C1511 back to its original voltage and circuit is ready to be
triggered by the next TE pulse. The brief pulse that results at U1506-A’s
output while the capacitor voltage is below the threshold voltage is OR-
ed with the global reset signal, INITe, in U1507-D. The result is DTE,
which forces PULSE_DWF back to the low state to end the pulse.
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