Alinx ARTIX-7 - Page 35

ARTIX-7 FPGA Development Board AX7101 User Manual
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The 1
st
channel Gigabit Ethernet pin assignments are as follows：
Signal Name
FPGA Pin
Description
E1_GTXC
G21
Ethernet GMII transmit clock
E1_TXD0
D22
Ethernet Transmit Data bit0
E1_TXD1
H20
Ethernet Transmit Data bit1
E1_TXD2
H22
Ethernet Transmit Data bit2
E1_TXD3
J22
Ethernet Transmit Data bit3
E1_TXD4
K22
Ethernet Transmit Data bit4
E1_TXD5
L19
Ethernet Transmit Data bit5
E1_TXD6
K19
Ethernet Transmit Data bit6
E1_TXD7
L20
Ethernet Transmit Data bit7
E1_TXEN
G22
Ethernet transmit enable signal
E1_TXER
K17
Ethernet transmit error signal
E1_TXC
K21
Ethernet GMII transmit clock
E1_RXC
K18
Ethernet GMII receive clock
E1_RXDV
M22
Ethernet receive data valid signal
E1_RXER
N18
Ethernet receiving data error
E1_RXD0
N22
Ethernet Receive Data Bit0
E1_RXD1
H18
Ethernet Receive Data Bit1
E1_RXD2
H17
Ethernet Receive Data Bit2
E1_RXD3
M21
Ethernet Receive Data Bit3
E1_RXD4
L21
Ethernet Receive Data Bit4
E1_RXD5
N20
Ethernet Receive Data Bit5
E1_RXD6
M20
Ethernet Receive Data Bit6
E1_RXD7
N19
Ethernet Receive Data Bit7
E1_COL
M18
Ethernet Collision signal
E1_CRS
L18
Ethernet Carrier Sense Signal
E1_RESET
G20
Ethernet Reset Signal
E1_MDC
J17
Ethernet Management Clock
E1_MDIO
L16
Ethernet Management Data