Alinx ARTIX-7 - Page 36

ARTIX-7 FPGA Development Board AX7101 User Manual
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The 2
nd
channel Gigabit Ethernet pin assignments are as follows：
Signal Name
FPGA Pin
Description
E2_GTXC
M16
Ethernet GMII transmit clock
E2_TXD0
L15
Ethernet Transmit Data bit0
E2_TXD1
K16
Ethernet Transmit Data bit1
E2_TXD2
W15
Ethernet Transmit Data bit2
E2_TXD3
W16
Ethernet Transmit Data bit3
E2_TXD4
V17
Ethernet Transmit Data bit4
E2_TXD5
W17
Ethernet Transmit Data bit5
E2_TXD6
U15
Ethernet Transmit Data bit6
E2_TXD7
V15
Ethernet Transmit Data bit7
E2_TXEN
M15
Ethernet transmit enable signal
E2_TXER
T15
Ethernet sends an error signal
E2_TXC
T14
Ethernet GMII transmit clock
E2_RXC
J20
Ethernet GMII receive clock
E2_RXDV
L13
Ethernet receive data valid signal
E2_RXER
G13
Ethernet receiving data error
E2_RXD0
M13
Ethernet Receive Data Bit0
E2_RXD1
K14
Ethernet Receive Data Bit1
E2_RXD2
K13
Ethernet Receive Data Bit2
E2_RXD3
J14
Ethernet Receive Data Bit3
E2_RXD4
H14
Ethernet Receive Data Bit4
E2_RXD5
H15
Ethernet Receive Data Bit5
E2_RXD6
J15
Ethernet Receive Data Bit6
E2_RXD7
H13
Ethernet Receive Data Bit7
E2_COL
J11
Ethernet Collision signal
E2_CRS
E22
Ethernet Carrier Sense Signal
E2_RESET
L14
Ethernet Reset Signal
E2_MDC
AB21
Ethernet Management Clock
E2_MDIO
AB22
Ethernet Management Data