Alinx ARTIX-7 - Page 37

ARTIX-7 FPGA Development Board AX7101 User Manual
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The 3
rd
channel Gigabit Ethernet pin assignments are as follows：
Signal Name
FPGA Pin
Description
E3_GTXC
AA21
Ethernet GMII transmit clock
E3_TXD0
W11
Ethernet Transmit Data bit0
E3_TXD1
W12
Ethernet Transmit Data bit1
E3_TXD2
Y11
Ethernet Transmit Data bit2
E3_TXD3
Y12
Ethernet Transmit Data bit3
E3_TXD4
W10
Ethernet Transmit Data bit4
E3_TXD5
AA11
Ethernet Transmit Data bit5
E3_TXD6
AA10
Ethernet Transmit Data bit6
E3_TXD7
AB10
Ethernet Transmit Data bit7
E3_TXEN
V14
Ethernet transmit enable signal
E3_TXER
AA9
Ethernet sends an error signal
E3_TXC
V10
Ethernet GMII transmit clock
E3_RXC
V13
Ethernet GMII receive clock
E3_RXDV
AA20
Ethernet receive data valid signal
E3_RXER
U21
Ethernet receiving data error
E3_RXD0
AB20
Ethernet Receive Data Bit0
E3_RXD1
AA19
Ethernet Receive Data Bit1
E3_RXD2
AA18
Ethernet Receive Data Bit2
E3_RXD3
AB18
Ethernet Receive Data Bit3
E3_RXD4
Y17
Ethernet Receive Data Bit4
E3_RXD5
W22
Ethernet Receive Data Bit5
E3_RXD6
W21
Ethernet Receive Data Bit6
E3_RXD7
T21
Ethernet Receive Data Bit7
E3_COL
Y21
Ethernet Collision signal
E3_CRS
Y22
Ethernet Carrier Sense Signal
E3_RESET
T20
Ethernet Reset Signal
E3_MDC
V20
Ethernet Management Clock
E3_MDIO
V19
Ethernet Management Data