Alinx ARTIX-7 - Page 38

ARTIX-7 FPGA Development Board AX7101 User Manual
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The 4
th
channel Gigabit Ethernet pin assignments are as follows：
Signal Name
FPGA Pin
Description
E4_GTXC
P20
Ethernet GMII transmit clock
E4_TXD0
R17
Ethernet Transmit Data bit0
E4_TXD1
P15
Ethernet Transmit Data bit1
E4_TXD2
N17
Ethernet Transmit Data bit2
E4_TXD3
P17
Ethernet Transmit Data bit3
E4_TXD4
T16
Ethernet Transmit Data bit4
E4_TXD5
U17
Ethernet Transmit Data bit5
E4_TXD6
U18
Ethernet Transmit Data bit6
E4_TXD7
P19
Ethernet Transmit Data bit7
E4_TXEN
P16
Ethernet transmit enable signal
E4_TXER
R19
Ethernet sends an error signal
E4_TXC
U16
Ethernet GMII transmit clock
E4_RXC
Y18
Ethernet GMII receive clock
E4_RXDV
W20
Ethernet receive data valid signal
E4_RXER
N13
Ethernet receiving data error
E4_RXD0
W19
Ethernet Receive Data Bit0
E4_RXD1
Y19
Ethernet Receive Data Bit1
E4_RXD2
V22
Ethernet Receive Data Bit2
E4_RXD3
U22
Ethernet Receive Data Bit3
E4_RXD4
T18
Ethernet Receive Data Bit4
E4_RXD5
R18
Ethernet Receive Data Bit5
E4_RXD6
R14
Ethernet Receive Data Bit6
E4_RXD7
P14
Ethernet Receive Data Bit7
E4_COL
N14
Ethernet Collision signal
E4_CRS
N15
Ethernet Carrier Sense Signal
E4_RESET
R16
Ethernet Reset Signal
E4_MDC
V18
Ethernet Management Clock
E4_MDIO
U20
Ethernet Management Data