AlphaTheta DJM-V10 - Page 19

19
DJM-V10
5
6 7 8
5
6 7 8
A
B
C
D
E
F
Handshake request
Handshake permission
CLKGEN1_OEB [HIGH]
Setting
ADC XRST/DAC XRST [HIGH]
V+15A_CONT control instructions
V+15A_CONT [HIGH]
LCD_XRST [HIGH]
LCD setting
V+12LCDBL_CONT control instructions
V+12LCDBL_CONT [HIGH]
D-IN_SRC XRST [HIGH]
DIR_XRST [HIGH]
DIT_XRST [HIGH]
MCLK_EN [HIGH]
MFI_XRST [HIGH]
USBPSW_EN [HIGH]
Handshake request
Handshake permission
LAN reset completion notice
SDSP start instructions
Program transmission
SDSP_XRST [HIGH]
Start completion notice
SDSP start completion notice
DSP start instructions
Start completion notice
LinkCue handshake request
LinkCue handshake permission
Start completion notice
MUTE_OUT [HIGH]
Software muting canceling
A terminal
VBAS output start
Digital INSRC canceling
ADC/DAC setting
DSP program road
DSP reset canceling
BOOT
USBPSW_FA ON
CLK_GEN
AUDIO_CLK
BOOT
MUTE canceling
3000 ms (noise measures)
ADC, DAC reset canceling
V+12LCDBL_CONT ON
DSS Initialization
LCD reset canceling
DIT reset canceling
DIT setting
DIR setting
MFI IC Initialization
MFI IC reset canceling
USB Initialization
V+15A_CONT ON
DIT reset canceling
SUB DSP(SRC)
(D810)
USB/ETHER UCOM
(AM3352)
Power supply Clock generator
PNL2 UCOM
(M16C)
MAIN CPU/DSP(CPU)
(66AK)
MAIN CPU/DSP(DSP)
(66AK)
PNL1 UCOM
(M16C)
A