AlphaTheta DJM-V10 - DIAGNOSIS; POWER ON SEQUENCE

18
DJM-V10
1
2 3 4
A
B
C
D
E
F
1
2 3 4
5. DIAGNOSIS
5.1 POWER ON SEQUENCE
: GPIO : UART : I2C
: SPI : HPI
Canceling reset [HIGH]
VMUTE_CONT [HIGH]
DIGIP_CON [HIGH]
V+5D_MDSP_CONT [HIGH]
V+1R285D_CONT [HIGH]
V+3R3D_MDSP_CONT [HIGH]
V+3R8D_AM_CONT [HIGH]
V+3R3D_CONT [HIGH]
MDAC_V_CONT [HIGH]
V+2R5D_CONT [HIGH]
PMIC_MDSP_XRST [HIGH] Auto from 66AK PMIC
PMIC_AM_XRST [HIGH] Auto from AM PMIC
MDSP_xRST [HIGH]
AM_XRST [HIGH]
MDSP_OFF [HIGH]
UPD_PNL1_MDSP [LOW]
MDSP_OFF [LOW]
AM_MDSP_XINT [HIGH]
UPD_MDSP_AM [LOW]
V+15A_CONT [HIGH]
RST_PNL1_PNL2 [HIGH]
Handshake permission
Handshake request
V+5D_CONT
[HIGH]
DDR 3_RESETn [HIGH]
DDR _XRST [HIGH]
AM_OFF [HIGH]
LAN_XRESET [HIGH]
SUB DSP(SRC)
(D810)
USB/ETHER UCOM
(AM3352)
Power supply Clock generator
PNL2 UCOM
(M16C)
MAIN CPU/DSP(CPU)
(66AK)
MAIN CPU/DSP(DSP)
(66AK)
PNL1 UCOM
(M16C)
VMUTE ON
V+12E ON
Hardware contents
Software contents
[PANEL_CLK] ON
BOOT/Initialization
194.4 ms
V+3R3E ON
[DIGIP_CON] ON
30 ms
V+3R3D_MDSP_CONT ON
V+5D_MDSP_CONT ON
SYSOSC_CLK
(24M)
1st BOOT
2nd BOOT start
40 ms
Mode judgment
DDR3 reset canceling
Key decision wait(? ms)
KEY VR read start
3rd BOOT
V+3R8D_AM_CONT ON
AM_PLL_24M
50M_PHY_CLK
LANPHY reset canceling
SDSP_PLL_24M
V+5D_CONT ON
V+2R5D_CONT ON
V+15A_CONT ON
MDAC_V_CONT ON
V+1R285D_CONT ON
5 ms
V+3R3D_CONT ON
5 ms
5 ms
1st BOOT
2nd BOOT
40 ms
10 ms
BOOT/Initialization
VMUTE_CONT ON
A
DDR3 reset canceling