P54x/EN FD/La4 Firmware Design
(FD) 9-6
MiCOM P543, P544, P545 & P546
FD
2. HARDWARE MODULES
The relay is based on a modular hardware design where each module performs a separate
function within the relay operation. This section describes the functional operation of the
various hardware modules.
2.1 Processor board
The
relay is based around a TMS320VC33-150 MHz (peak speed), floating point, 32-bit
digital signal processor (DSP) operating at a clock frequency of half this speed. This
processor performs all of the calculations for the relay, including the protection functions,
control of the data communication and user interfaces including the operation of the LCD,
keypad and LEDs.
The processor board is located directly behind the relay’s front panel which allows the LCD
and LEDs to be mounted on the processor board along with the front panel communication
ports. These comprise the 9-pin D-connector for EIA(RS)232 serial communications
(e.g. using MiCOM S1 Studio and Courier communications) and the 25-pin D-connector
relay test port for parallel communication. All serial communication is handled using a field
programmable gate array (FPGA).
The memory provided on the main processor board is split into two categories, volatile and
non-volatile: the volatile memory is fast access SRAM which is used for the storage and
execution of the processor software, and data storage as required during the processor’s
calculations. The non-volatile memory is sub-divided into 2 groups: 4 MB of flash memory
for non-volatile storage of software code, text and configuration data including the present
setting values, and 2 MB of battery backed-up SRAM for the storage of disturbance, event,
fault and maintenance record data.
2.2 Co-processor board
A second p
rocessor board is used in the relay for the processing of the current differential
and distance protection algorithms. The processor used on the second board is the same as
that used on the main processor board. The second processor board has provision for fast
access (zero wait state) SRAM for use with both program and data memory storage. This
memory can be accessed by the main processor board via the parallel bus, and this route is
used at power-on to download the software for the second processor from the flash memory
on the main processor board. Further communication between the two processor boards is
achieved via interrupts and the shared SRAM. The serial bus carrying the sample data is
also connected to the co-processor board, using the processor’s built-in serial port, as on the
main processor board.
The co-processor board also handles all communication with the remote differential relay(s).
This is achieved via BFOC 2.5 – ST optical fiber connections at the rear and hence the co-
processor board holds the optical modules to transmit and receive data over the fiber links.
One or two channels will be provided, each comprising a Rx (receive) and a Tx (transmit)
fiber as a pair. The channels, when fitted according to an ordering option, are labeled Ch1
and Ch2.
2.3 Internal communication buses
The
relay has two internal buses for the communication of data between different modules.
The main bus is a parallel link that is part of a 64-way ribbon cable. The ribbon cable carries
the data and address bus signals in addition to control signals and all power supply lines.
Operation of the bus is driven by the main processor board that operates as a master while
all other modules within the relay are slaves.
The second bus is a serial link that is used exclusively for communicating the digital sample
values from the input module to the main processor board. The DSP processor has a built-in
serial port that is used to read the sample data from the serial bus. The serial bus is also
carried on the 64-way ribbon cable.
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