Alstom MiCOM P546 - 3.4.3.2 Distance protection; 3.4.3.3 Fourier filtering; 3.4.4 Programmable scheme logic

Firmware Design P54x/EN FD/La4
MiCOM P543, P544, P545 & P546
(FD) 9-17
3.4.3.2 Distance protection
The cu
rrent and voltage inputs are filtered, using finite impulse response (FIR) digital filters
to reduce the effects of non-power frequency components in the input signals, such as DC
offsets in current waveforms, and capacitor voltage transformer (CVT) transients in the
voltages. The P54x uses a combination of a 1/4 cycle filter using 12 coefficients, a 1/2 cycle
filter using 24 coefficients, and a one cycle filter using 48 coefficients. The relay
automatically performs intelligent switching in the application of the filters, to select the best
balance of removal of transients with fast response. Note that the protection elements
themselves then perform additional filtering, for example implemented by the trip count
strategy.
Figure 7 shows the frequency response of the 12, 24 and 48
coefficient filters, noting that all
have a gain of unity at the fundamental:
Filter Response
0
0.5
1
1.5
2
2.5
0 369 12 15 18 21
Harmonic
Gain
Full
Half
Quarter
P1305ENa
Figure 7 Frequency response of filters
3.4.3.3 Fourier filtering
All b
ackup protection and measurement functions use one cycle fourier digital filtering to
extract the power frequency component. This filtering is performed on the main processor
board.
FD
3.4.4 Programmable scheme logic
The pu
rpose of the programmable scheme logic (PSL) is to allow the relay user to configure
an individual protection scheme to suit their own particular application. This is achieved
through the use of programmable logic gates and delay timers. To allow greater flexibility
the PSL is part of the relay protection setting group.
The input to the PSL is any combination of the status of the digital input signals from the
opto-isolators on the input board, the outputs of the protection elements, e.g. protection
starts and trips, and the outputs of the fixed protection scheme logic. The fixed scheme logic
provides the relay’s standard protection schemes. The PSL itself consists of software logic
gates and timers. The logic gates can be programmed to perform a range of different logic
functions and can accept any number of inputs. The timers are used either to create a
programmable delay, and/or to condition the logic outputs, e.g. to create a pulse of fixed
duration on the output regardless of the length of the pulse on the input. The outputs of the
PSL are the LEDs on the front panel of the relay and the output contacts at the rear.