Preliminary Technical Data UG-1828
Rev. PrC | Page 21 of 338
Functionality Constrains and Limitations
must ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
FDPD The DPD functionality is not available when ADRV9001 operates in 1T1R mode.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. The maximum input signal amplitude must not exceed −82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence, user needs to ensure that Power Amplifier is
powered down to avoid unwanted emission of Tx calibration tones at the antenna.
For Tx tracking calibrations to operate, ADRV9001 needs to access Rx datapath during Tx time slots to operate.
AGPIOs Analog GPIOs (operating at 1.8 V level) can be used as read or write digital levels of in the end user system. AGPIOs
can be used to control states of external components (for example, RF Switch) or read back digital logic levels from
external components.
DGPIOs For DMR type applications, ADRV9001 supports RF Monitor mode of operation. DGPIO pins are used to: sent wake up
signal to baseband processor, allow baseband processor to move ADRV9001 into Monitor mode using hardware pins
(instead API command).
Digital GPIOs can also be used to perform real-time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 2 GPIOs may be used by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (for example, temperature sensor). AuxADC input voltage must not
exceed 0.9 V.
AuxDAC AuxDAC can be used to control the VCXO responsible for generating the ADRV9001 device clock, generate pre-
configured ramp up/down signal that can be used to control power amplifier bias, control any circuitry that requires
analog control voltage up to 1.8 V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, the ADRV9001 can be initialized using API functions only.
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