Preliminary Technical Data UG-1828
Rev. PrC | Page 225 of 338
functionality can be assigned DGPIO_14 and DGPIO_15 when it is in LVDS mode, or either of DGPIO_14 or DGPIO_15 can be used as
the Tx1 DCLK out if it is in CMOS mode.
Noted, when Tx DCLK OUT function is disabled, the corresponding DGPIOs (DGPIO12/13 or DGPIO 14/15) can only be reused as
input function.
ANALOG GPIO OPERATION
The main purpose of the Analog GPIO pins is to serve as control pins for the external control elements, such as a Digital Step Attenuator
(DSA), Low Noise Amplifier (LNA), external LO/VCO components, T/R switch of TDD system, and so on. An alternative function of
some Analog GPIO pins are to provide the auxiliary DAC output.
A high level overview of the analog GPIO features are provided in Table 88.
Table 89. Summary of Analog GPIO Features
Feature Description GPIO Pins Available for Feature
RX Gain Table
External Control
Word
The RX gain table can include a column for 2-bit control of an
external gain element (LNA), each Rx channel has 2 Analog
GPIO pins associated with it.
Any Analog GPIO, but Rx1/Rx2 external gain
word must be in one AGPIO nibble
RF Front-End Control Allow AGPIO timing to be associated with Tx/Rx_Enable to
control the RF Front End
AGPIO_0 for Tx1
AGPIO_1 for Rx1
AGPIO_8 for Tx2
AGPIO_9 for Rx2
Manual Pin Toggle Manual control the GPIO output level, API functions sets
output pin levels and reads the input pin levels
Any Analog GPIO
Auxiliary DAC Output Allow the auxiliary DAC output on analog GPIO pins AGPIO_0: AuxDAC0 output pin select
AGPIO_1: AuxDAC1 output pin select
AGPIO_2: AuxDAC2 output pin select
AGPIO_3: AuxDAC3 output pin select
RX Gain Table External Control Word
A complete description of RX Gain Table external control is provided in the Receiver Gain Control section in this User Guide.
External LNA gain can be controlled by ADRV9001 AGPIO output, each channel has 2 AGPIO control signals and achieve up to 4
external LNA gain steps control. The external LNA gain control can be enabled and configured by
adi_adrv9001_Rx_ExternalLna_Configure().
The AGPIOs for channel1 and channel 2 must be in one AGPIO nibble, which means the 4 AGPIO for external gain control has to be
AGPIO[3:0] or AGPIO[7:4] or AGPIO[11:8]. For example, AGPIO_7/AGPIO_6 for Rx1 external gain control, AGPIO_5/AGPIO_4 for
Rx2.
RF Front-End Control
To save the baseband processor control pins, ADRV9001 provides the function to output control signals via analog GPIO pins to power
up/down the external RF front end components (i.e. LNA, TX Gain blocks, Ext PLL) or switch the T/R switch of a TDD system. For
example, a TX_On, RX_ON output signal through the analog GPIOs and associated with the ADRV9001 Tx/Rx Enable timing and state
can be used to enable/disable the power amplifier and LNA respectively, or do the antenna switch.
To get the best timing control performance, the dedicated AGPIOs are assigned for Tx/Rx front end control, AGPIO_0, AGPIO_1,
AGPIO_8, AGPIO_9 are associated with Tx1_Enable, Rx1_Enable, Tx2_Enable, Rx2_Enable respectively.
The AGPIO for external RF front end control is initialized in adi_adrv9001_gpio_ControlInit_Configure(), and the relative AGPIOs are
configured by API adi_adrv9001_gpio_Configure().
Noted, once the AGPIO external RF front end control is enabled, the Rx Gain table external control can only use AGPIO[7:4].
Manual Pin Toggle
Similar with the manual pin toggle for digital GPIOs, this feature allows control of the logic level of individual analog GPIO pins, the
adi_adrv9001_gpio_ManualAnalogOutput_Configure() and adi_adrv9001_gpio_ManualAnalogInput_Configure () is used to configure
the Analog GPIO to manually output and input mode respectively. adi_adrv9001_gpio_OutputPinLevel_Set() and
adi_adrv9001_gpio_InputPinLevel_Get() can be used to set and read relative analog GPIO level respectively.
Users can use the manual AGPIO level toggle to control external RF components, like power up/down the PA, etc.
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