Preliminary Technical Data UG-1828
Rev. PrC | Page 29 of 338
Radar Type Application Overview
With a minimum number of external components, the ADRV9001 transceiver can be used to build complete RF-to-bits signal chain that
can serve as RF front end building block in Radar type applications. ADRV9001 internal AGC can be used to autonomously monitor and
set the appropriate gain level for Rx signal chains. Internal AGC can use analog GPIO interface to control external DSA in the Rx signal
chains. For time critical TDD type applications control of the ADRV9001 TRx can be done by toggling control lines. ADRV9001 can
control external Rx/Tx switch using its analog GPIOs as well as provide power amplifier bias voltage by utilizing AuxDAC outputs. Multi
Chip Sync signal together with DEV_CLK can be used to synchronize multiple ADRV9001 in the end system.
Table 10. Constrains and Limitations in Radar Type Application
Functionality Constrains and Limitations
Rx Signal Path The user must ensure that appropriate level of isolation between Rx1 and Rx2 as well as Rx to Tx is provided at the
system level. In the previously described example, RxB input is used during Tx observation. The LNA connected to the
Rx1A should be powered down during Tx slots to ensure proper operation of the Tx observation path (connected to
the Rx1B). The user must ensure that appropriate attenuation is present in line to prevent Rx input being overloaded
by Tx signal.
In Radar type application, ADRV9001 can use its internal LO to generate RF LO1 for both uplink and downlink. For
applications with stringent RF LO requirements, user can use external LO inputs. External LO1 operating at 2× RF LO
can be used for both uplink and downlink.
RF Front End For LO generation, the ADRV9001 uses internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as
high as −50 dBc and 3rd harmonic can be as high as −9 dBc. Therefore, the RF filtering on the Rx and Tx path must
ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
DPD The DPD functionality can be used in the 2R2T TDD mode. Maximum channel bandwidth that DPD can support is
limited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can be performed by ADRV9001 or ORx
data can be sent to baseband processor via Rx data port during Tx operation. Rx path used during DPD operation to
perform Tx observation is also used by the Tx tracking calibrations. In case of external DPD, user must ensure that
access to the Rx path during Tx slots is time-shared between DPD operation and Tx calibrations.
Calibrations During Rx initialization sequence user must ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. The maximum input signal amplitude must not exceed −82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence the user must ensure that the power amplifier is
powered down to avoid unwanted emission of Tx calibration tones at the antenna.
ADRV9001 must access Rx datapath during Tx time slots for Tx tracking calibration to operate. If user use DPD in its
system then access to Rx datapath during Tx slots must be time-shared between DPD operation and Tx calibrations.
AGPIOs Analog GPIOs (operating at 1.8 V level) can be used as read or write digital levels of in the end user system. AGPIOs
can be used to control states of external components (for example, RF Switch) or read back digital logic levels from
external components.
DGPIOs Digital GPIOs can be used to perform real-time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be used by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (for example, temperature sensor). Maximum AuxADC input voltage
must not exceed 0.9 V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating Device clock, generate pre-configured ramp
up/down signal that can be used to control power amplifier bias, control any circuitry that requires analog control
voltage up to 1.8 V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync ADRV9001 allows the user to synchronize multiple transceivers used in single system. ADRV9001 provides the
capability to accept an external reference clock and synchronize operation with other devices using simple control
logic. Logical pulses applied at MCS input align each device’s data clock with a common reference. Relationship of
MCS pulse to the DEV_CLK edge at the ADRV9001 pins must be preserved. For correct operation, it is critical to match
the length of PCB traces that carry DEV_CLK and MCS signals to each ADRV9001 device.
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