Analog Devices ADRV9001

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Preliminary Technical Data UG-1828

Rev. PrC | Page 291 of 338

Figure 269. Xilinx Evaluation Board with Jumper Settings and Switch Position Configured to Work with ADRV9001 Evaluation Platform

24159-300

Main Page

Table of Contents2
How to Use this Document5
Block Diagram6
Product Highlights7
- Adrv90027
- Bandwidth and Sample Rate Support7
- Adrv90039
- Adrv90049
ADRV9001 Example Use Cases10
- ADRV9001 in a Single-Band 2RT2R FDD Type Small-Cell Application10
- ADRV9001 in Dual-Band 2RT2R FDD Type Small-Cell Application12
- ADRV9001 in Single-Band 2T2R TDD Type Small-Cell Application14
- ADRV9001 in 1T1R FDD with DPD Type Application16
- ADRV9001 in TETRA Type Portable Radio Application18
- ADRV9001 in DMR Type Portable Radio Application20
- ADRV9001 in FDD Type Repeater Application22
- ADRV9001 in a FDD Type Repeater Application Using Internal Loopbacks24
- ADRV9001 in TDD Type Repeater Application26
- ADRV9001 in Radar Type Application28
Software System Architecture Description30
- Software Architecture30
- Folder Structure31
Customising the System Architecture and File Structure32
Software Integration35
- Hardware Abstraction Layer35
- Developing the Application41
System Initialization and Shutdown43
- TES Configuration and Initialization43
- API Initialization Sequence44
- Shutdown Sequence46
Serial Peripheral Interface (SPI)47
- SPI Configuration47
- SPI Bus Signals48
- SPI Data Transfer Protocol48
- Timing Diagrams50
- SPI Test51
Data Interface52
- General Description52
- Electrical Specification52
- CMOS Synchronous Serial Interface (CMOS-SSI)54
- LVDS Synchronous Serial Interface (LVDS-SSI)61
- Enhanced Rx SSI Mode64
- Power Saving for LSSI65
- SSI Timing Parameters65
- API Programming65
- CSSI/LSSI Testability and Debug68
Microprocessor and System Control70
- System Control71
- Timing Parameters Control71
Clock Generation86
Multichip Synchronization88
- Introduction88
- Theory of Operation88
- MCS Substates (Internal MCS State Transition)91
- Procedure91
- Sample Delay and Read Delay92
- Phase Synchronization94
Synthesizer Configuration and lo Operation96
- Clock Synthesizer96
- RF Synthesizer96
- Auxiliary Synthesizer97
- External lo97
- API Operation99
Frequency Hopping102
- Key Signals102
- Modes of Operation105
- Channel and Profile Selection106
- Frequency Hopping Operation Ranges107
- Frequency Hopping Table107
- Frequency Hopping Calibrations111
- Frequency Hopping Timing113
- Additional Frequency Hopping Operations117
- Diversity Mode121
- Frequency Hopping with Rx/Orx Gain Control121
- Integration with Other Advanced Features122
Transmitter Signal Chain123
- Data Interface123
- Datapath124
- Digital Front End (DFE)124
- Analog Front End (AFE)129
- Transmit Data Chain API Programming130
Receiver/Observation Receiver Signal Chain131
- Receive Data Chain133
- Analog Front-End Components134
- Lpf135
- Adc135
- Digital Front End Components136
- DC Offset136
- Qec137
- DDC137
- Frequency Offset Correction137
- Pfir137
- Rssi137
- Receive Data Chain API Programming138
Transmitter/Receiver/Observation Receiver Signal Chain Calibrations140
- Initial Calibrations140
- Tracking Calibrations150
Receiver Gain Control154
- Receiver Datapath155
- Gain Control Modes158
- Gain Control Detectors166
- AGC Clock and Gain Block Timing169
- Analog Gain Control API Programming170
- Digital Gain Control and Interface Gain (Slicer)177
- Digital Gain Control and Interface Gain API Programming179
- Usage Recommendations180
- TES Configuration and Debug Information181
Rx Demodulator184
- Rx Narrow-Band Demodulator Subsystem184
- Normal IQ Output Mode188
- Frequency Deviation Output Mode188
- API Programming189
Power Saving and Monitor Mode191
- Power-Down Modes191
- Power-Down/Power-Up Channel in Calibrated State192
- Dynamic Interframe Power Saving192
- Monitor Mode194
Digital Predistortion197
- Background197
- ADRV9001 DPD Function197
- ADRV9001 DPD Supported Waveforms199
- DPD with Frequency Hopping (FH)199
- ADRV9001 DPD Performance199
- Closed Loop Gain Control (CLGC)201
- DPD/CLGC Configuration201
- Board Configuration210
- Save and Load DPD Coefficients from Last Transmission211
- Define the Frequency Region When Performing DPD with FH211
- DPD/CLGC API Programming212
- DPD Tuning and Testing212
- CLGC Target Gain Measurment215
Dynamic Profile Switching216
- Overview216
- Initial Calibration with DPS216
- Perform DPS on the Fly217
- DPS API Programming218
- Summary of DPS Limitations218
- DPS Operations in TES219
General-Purpose Input/Output and Interrupt Configuration221
- Digital GPIO Operation222
- Analog GPIO Operation225
- Interrupt226
Auxiliary Converters and Temperature Sensor227
- Auxiliary DAC (Auxdac)227
- Auxiliary ADC (Auxadc)227
- Temperature Sensor228
RF Port Interface Information229
- Transmit Ports: TX1± and TX2229
- Receive Ports: RX1A±, RX1B±, RX2A±, and RX2B229
- External lo Ports: LO1± and LO2229
- Device Clock Port: DEV_CLK1229
- RF Rx/Tx Ports Impedance Data229
- General Receiver Port Interface232
- General Transmitter Bias and Port Interface234
- Impedance Matching Network Examples236
- Receiver RF Port Impedance Matching Network236
- Receiver RF Port Impedance Match Measurement Data239
- Transmitter RF Port Impedance Matching Network241
- Transmitter RF Port Impedance Match Measurement Data242
- External lo Port Impedance Matching Network243
- External lo Impedance Match Measurement Data246
- Connection for External Device Clock (DEV_CLK_IN)247
- DEV_CLK_IN Phase Noise Requirements249
- Connection for Multichip Synchronization (MCS) Input250
Printed Circuit Board Layout Recommendations251
- PCB Material and Stack up Selection251
- Fan-Out and Trace Space Guidelines252
- Component Placement and Routing Priorities253
- RF and Data Port Transmission Line Layout259
- Isolation Techniques Used on the ADRV9001 Evaluation Card266
Power Supply Recommendations269
Power Management Considerations269
- Power Supply Sequence269
- Power Supply Domain Connections270
- Power Supply Architecture272
- RF and Clock Synthesizer Supplies275
Power Supply Configurations276
Summary282
LDO Configurations283
ADRV9001 Evaluation System290
- Initial Setup290
- Hardware Kit290
- Hardware Operation295
- Transceiver Evaluation Software (TES)296
- Automated Time Division Duplexing (TDD)317
- Tracking Calibrations320
- Digital Predistortion321
- TDD Enablement Delays321
- Auxiliary DAC/ADC321
- Frequency Hopping TES Examples322
- Radio State331
- Power/Temperature Monitoring331
- Driver Debugger332
- Log File333
- Automatically Generate Initialisation Code334
- Evaluation System Troubleshooting334

Analog Devices ADRV9001

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