Asus P5VDC-TVM SE - DRAM Timing Selectable [By SPD]; Memory Hole [Disabled]; Primary Display Adapter [Pci_E]; VGA Share Memory Size [64 MB]

ASUS P5VDC-TVM SE 2-13
2.5.4 DRAM Timing Selectable [By SPD]
When this item is set to [By SPD], the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When set to [Manual], you can
manually set the DRAM timing parameters through the DRAM sub-items. The
following sub-items appear when this item is set to [Manual]. Conguration options:
[Manual] [By SPD]
CAS Latency Time [3]
Controls the latency between the DRAM read command and the time the data
actually becomes available. Conguration options when installing DDR memory
modules: [2] [2.5] [3]; Conguration options when installing DDR2 memory
modules: [2] [3] [4] [5]
Bank Interleave [4 Bank]
Conguration options: [Disabled] [2 Bank] [4 Bank] [8 Bank]
Precharge to Active (Trp) [3T ]
Conguration options: [2T] [3T] [4T] [5T]
Active to Precharge (Tras) [09T]
Conguration options: [05T] ~ [20T]
Active to CMD (Trcd) [3T]
Conguration options: [2T] [3T] [4T] [5T]
2.5.5 Memory Hole [Disabled]
Allows you to reserve an address for ISA expansion cards.
Conguration options: [Disabled] [15M-16M]
2.5.6 Primary Display Adapter [PCi-E]
Conguration options: [PCI] [PCI-E]
2.5.7 VGA Share Memory Size [64MB]
Allows you to select the size of VGA Share Memory.
Conguration options: [Disabled] [16MB] [32MB] [64MB]