Atmel AT90S2313 - Page 16

AT90S2313
16
Figure 21. Single Cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.
Figure 22. On-Chip Data SRAM Access Cycles
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
System Clock Ø
WR
RD
Data
Data
Address
Address
T1 T2 T3 T4
Prev. Address
Read Write