Atmel AT90S2313 - Page 49

AT90S2313
49
Port B Schematics
Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.
Figure 38. Port B Schematic Diagram (pins PB0 and PB1)
Figure 39. Port B Schematic Diagram Pin PB3
PB3
DDB3
MOS
PULL-
UP
RESET
R
Q
D
C
RD
WD
WP
COM1A0
COM1A1
COMP. MATCH1
OUTPUT
MODE SELECT
RESET
R
Q
D
C
PORTB3
RL
RP
WP: WRITE PORTB
WD: WRITE DDRB
RL: READ PORTB LATCH
RP: READ PORTB PIN
RD: READ DDRB
DATA BUS