AT90S4414/8515
21
Reset Sources
The AT90S4414/8515 has three sources of reset:
• Power-On Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V
POT
).
• External Reset. The MCU is reset when a low level is present on the RESET
pin for more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.
During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The
instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the
program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at
these locations. The circuit diagram in Figure 23 shows the reset logic. Table 4 defines the timing and electrical parameters
of the reset circuitry.
Figure 23. Reset Logic
Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling).
The user can select the start-up time according to typical oscillator start-up. The number of WDT oscillator cycles used for
each time-out is shown in Table 5. The frequency of the watchdog oscillator is voltage dependent as shown in “Typical
Characteristics” on page 86.
Table 4. Reset Characteristics
Symbol Parameter Min Typ Max Units
V
POT
(1)
Power-on Reset Threshold Voltage (rising) 0.8 1.2 1.6 V
Power-on Reset Threshold Voltage (falling) 0.2 0.4 0.6 V
V
RST
RESET Pin Threshold Voltage - - 0.9 V
CC
V
t
TOUT
Reset Delay Time-out Period FSTRT Unprogrammed 11 16 21 ms
t
TOUT
Reset Delay Time-out Period FSTRT Programmed 1.0 1.1 1.2 ms
Table 5. Number of Watchdog Oscillator Cycles
FSTRT Time-out at V
CC
= 5V Number of WDT cycles
Programmed 1.1 ms 1K
Unprogrammed 16.0 ms 16K
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