23
AT90S2313
0839G–08/01
General Interrupt Mask
Register – GIMSK
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) defines whether the external
interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT1 is configured as an output. The corre-
sponding interrupt of External Interrupt Request 1 is executed from program memory
address $002. See also “External Interrupts”.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) defines whether the external
interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The corre-
sponding interrupt of External Interrupt Request 0 is executed from program memory
address $001. See also “External Interrupts.”
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S2313 and always read as zero.
General Interrupt FLAG
Register – GIFR
• Bit 7 – INTF1: External Interrupt Flag1
When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt
flag, INTF1, becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT1 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical “1” to it. The flag is always cleared when INT1 is configured
as level interrupt.
• Bit 6 – INTF0: External Interrupt Flag0
When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt
flag, INTF0, becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT0 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical “1” to it. The flag is always cleared when INT0 is configured
as level interrupt.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S2313 and always read as zero.
Note that external level interrupt does not have a flag, and will only be remembered for
as long as the interrupt condition is active.
Bit 7 6 5 4 3 2 1 0
$3B ($5B) INT1 INT0 – – – – – – GIMSK
Read/Write R/W R/W R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
$3A ($5A) INTF1 INTF0 – – – – – – GIFR
Read/Write R/W R/W R R R R R R
Initial value 0 0 0 0 0 0 0 0
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