20
AT90S2313
0839G–08/01
Figure 23. Reset Logic
Note: 1. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling).
The user can select the start-up time according to typical oscillator start-up. The number
of WDT oscillator cycles used for each time-out is shown in Table 4. The frequency of
the Watchdog Oscillator is voltage-dependent, as shown in “Typical Characteristics” on
page 75.
Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As
shown in Figure 23, an internal timer is clocked from the Watchdog Timer. This timer
prevents the MCU from starting until after a certain period after V
CC
has reached the
Power-on Threshold voltage (V
POT
) (see Figure 24). The FSTRT Fuse bit in the Flash
can be programmed to give a shorter start-up time if a ceramic resonator or any other
fast-start oscillator is used to clock the MCU.
If the built-in start-up delay is sufficient, RESET
can be connected to V
CC
directly or via
an external pull-up resistor. By holding the RESET
pin low for a period after V
CC
has
been applied, the Power-on Reset period can be extended. Refer to Figure 25 for a tim-
ing example of this.
Table 3. Reset Characteristics (V
CC
= 5.0V)
Symbol Parameter Min Typ Max Units
V
POT
(1)
Power-on Reset Threshold Voltage (rising) 1.0 1.4 1.8 V
Power-on Reset Threshold Voltage (falling) 0.4 0.6 0.8 V
V
RST
RESET Pin Threshold Voltage – 0.85 V
CC
V
t
TOUT
Reset Delay Time-out Period
FSTRT Unprogrammed
11.0 16.0 21.0 ms
t
TOUT
Reset Delay Time-out Period
FSTRT Programmed
0.25 0.28 0.31 ms
Table 4. Number of Watchdog Oscillator Cycles
FSTRT Time-out at V
CC
= 5V Number of WDT Cycles
Programmed 0.28 ms 256
Unprogrammed 16.0 ms 16K
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