25
AT90S2313
0839G–08/01
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Match Interrupt Enable) and the OCF1A are set (one), the
Timer/Counter1 Compare Match Interrupt is executed.
• Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the AT90S2313 and always read as zero.
• Bit 3 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit
and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture Interrupt is executed.
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2313 and always reads as zero.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0
(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the
Timer/Counter0 Overflow Interrupt is executed.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2313 and always reads as zero.
External Interrupts The External Interrupts are triggered by the INT1 and INT0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The External Interrupts
can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the MCU Control Register (MCUCR). When the External Interrupt is
enabled and is configured as level-triggered, the interrupt will trigger as long as the pin
is held low.
The External Interrupts are set up as described in the specification for the MCU Control
Register (MCUCR).
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles,
minimum. Four clock cycles after the interrupt flag has been set, the program vector
address for the actual interrupt handling routine is executed. During this 4-clock-cycle
period, the Program Counter (2 bytes) is pushed onto the stack, and the Stack Pointer is
decremented by 2. The vector is normally a relative jump to the interrupt routine, and
this jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (2 bytes) is popped back from the stack, the Stack
Pointer is incremented by 2, and the I-flag in SREG is set. When the AVR exits from an
interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
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