50
AT90S2313
0839G–08/01
Analog Comparator The Analog Comparator compares the input values on the positive input AIN0 (PB0) and
the negative input PB1(AIN1). When the voltage on the positive input PB0 (AIN0) is
higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Out-
put, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1
Input Capture function. In addition, the comparator can trigger a separate interrupt
exclusive to the Analog Comparator. The user can select interrupt triggering on compar-
ator output rise, fall or toggle. A block diagram of the comparator and its surrounding
logic is shown in Figure 37.
Figure 37. Analog Comparator Block Diagram
Analog Comparator Control
and Status Register – ACSR
• Bit 7 – ACD: Analog Comparator Disable
When this bit is set (one), the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power con-
sumption in active and idle modes. When changing the ACD bit, the Analog Comparator
Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can
occur when the bit is changed.
• Bit 6 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2313 and will always read as zero.
• Bit 5 – ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE
bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, ACI is cleared by
writing a logical “1” to the flag. Observe, however, that if another bit in this register is
modified using the SBI or CBI instruction, ACI will be cleared if it has become set before
the operation.
Bit 76543210
$08 ($28) ACD – ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial value 0 0 N/A 0 0 0 0 0
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