69
AT90S2313
0839G–08/01
Serial Downloading Both the program and data memory arrays can be programmed using the serial SPI bus
while RESET
is pulled to GND. The serial interface consists of pins SCK, MOSI (input)
and MISO (output). See Figure 53. After RESET
is set low, the Programming Enable
instruction needs to be executed first before program/erase instructions can be
executed.
Figure 53. Serial Programming and Verify
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction
and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-
tion turns the content of every memory location in both the program and EEPROM
arrays into $FF.
The program and EEPROM memory arrays have separate address spaces: $0000 to
$03FF for program Flash memory and $000 to $07F for EEPROM data memory.
Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low: > 2 XTAL1 clock cycle
High: > 2 XTAL1 clock cycles
Serial Programming
Algorithm
When writing serial data to the AT90S2313, data is clocked on the rising edge of SCK.
When reading data from the AT90S2313, data is clocked on the falling edge of SCK.
See Figure 54, Figure and Table 29 for timing details.
To program and verify the AT90S2313 in the Serial Programming Mode, the following
sequence is recommended (See 4-byte instruction formats in Table 28):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. If a crys-
tal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the
XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held
low during power-up. In this case, RESET
must be given a positive pulse of at least
two XTAL1 cycles duration after SCK has been set to “0”.
AT90S2313
VCC
2.7 - 6.0V
PB7
PB6
PB5
RESET
GND
XTAL1
SCK
MISO
MOSI
GND
CLOCK INPUT
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