18
AT90S2313
0839G–08/01
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction
Set description for detailed information.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
Stack Pointer – SP An 8-bit register at I/O address $3D ($5D) forms the stack pointer of the AT90S2313. 8
bits are used to address the 128 bytes of SRAM in locations $60 - $DF.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-
rupt stacks are located. This stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when
data is pushed onto the stack with the PUSH instruction, and it is decremented by 2
when an address is pushed onto the stack with subroutine calls and interrupts. The
Stack Pointer is incremented by 1 when data is popped from the stack with the POP
instruction, and it is incremented by 2 when an address is popped from the stack with
return from subroutine RET or return from interrupt RETI.
Reset and Interrupt
Handling
The AT90S2313 provides 10 different interrupt sources. These interrupts and the sepa-
rate reset vector each have a separate program vector in the program memory space.
All the interrupts are assigned individual enable bits that must be set (one) together with
the I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 (the External
Interrupt Request 0), etc.
Bit 76543210
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Table 2. Reset and Interrupt Vectors
Vector No. Program Address Source Interrupt Definition
1 $000 RESET
Hardware Pin, Power-on Reset and
Watchdog Reset
2 $001 INT0 External Interrupt Request 0
3 $002 INT1 External Interrupt Request 1
4 $003 TIMER1 CAPT1 Timer/Counter1 Capture Event
5 $004 TIMER1 COMP1 Timer/Counter1 Compare Match
6 $005 TIMER1 OVF1 Timer/Counter1 Overflow
7 $006 TIMER0 OVF0 Timer/Counter0 Overflow
8 $007 UART, RX UART, RX Complete
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