Avaya CS 1000 Series - Page 39

Providing clock referencing on the SILC
Complete the following procedure to provide clock referencing on the SILC.
Providing clock referencing on the SILC
To install the NTRB53 Clock Controller for CS 1000 refer to NN43001-301
1. Maintain the same polarity on each transmit and receive. Rewire the selected Tx
and Rx pairs (applicable to DSL0 and DSL1) to exchange the Tx and Rx pair
position. This rewiring is done at the Main Distribution Frame (MDF).
2. Remove the phantom power jumpers (two jumpers per DSL) from the pin
headers.
3. Place the SILC in the selected IPE slot.
4. Configure the selected DSL as Terminal Equipment (TE) mode in LD 27.
5. Enable the clock in LD 60 to output the clock references to the IPE back plane
pins.
6. Configure the Clock Controller card to accept ISDN BRI clock reference.
7. Check the appropriate messages from the Clock Controller to ensure that it is
synchronized to the proper clock reference in LD 60).
8. Connect the ISDN BRI clock reference cables to the Clock Controller, using the
procedures which follow.
Connecting clock reference cables
Complete this procedure to connect the ISDN BRI clock reference cables to the Clock
Controller. There are three different cables that route clock signals from the IPE back plane to
the Clock Controller face plate (as shown in
Figure 11: Clock reference cable connection on
page 40). Refer to Table 7: ISDN BRI clock reference tables on page 39.
Table 7: ISDN BRI clock reference tables
Code Length (feet) Use
NTND70AA 1.5 Connects IPE back plane to IPE I/
O panel.
NTND71AA-AD 6.5, 12, 25, 42 Connects IPE I/O to CE I/O panel.
NTND72AA 6.5 Connects CE I/O to Clock
Controller face plate.
Note:
Measure the distance between the IPE and CE modules to ensure that you order the correct
cable lengths.
Installing ISDN BRI hardware for trunk applications
ISDN Basic Rate Interface Installation and Commissioning March 2011 39