Connecting clock reference cables
1. Search for available D-sub 9 connector slots on the I/O panels of the selected IPE
and CE I/O modules (if the I/O panel is equipped with D-sub 9 connector slots). If
none is available, look for an empty slot used for 25-pair wire connectors (the cables
contain two adapter plates to convert a 25-wire slot to two D-sub 9 connector
slots).
2. Connect the cables as shown in
Figure 11: Clock reference cable connection on
page 40; if choosing IPE slots 0, 4, 8, or 12, remove the transmit and receive cable
installed on pins 72 - 79 and secure them to a proper place.
Figure 11: Clock reference cable connection
Clock recovery
The SILC is configured in the slave-slave mode when acting as a trunk interface. This is
configured through the Maintenance Signaling Channel (MSC). The microcontroller configures
the S/T chips on the SILC as appropriate.
The SILC can recover the network clock from the received data stream using on-chip phase
lock loops. The clock frequency that is recovered is 2.56 MHz. The jitter and wander conform
to CCITT recommendations.
All of the S/T chips on the SILC could be configured as Terminal Equipment Slaves (TES), but
only the clocks recovered from DSL0 and DSL1 are routed to the back plane connector pins.
These clocks are provided as differential pairs on back plane pins. See
Table 8: Clocks as
differential pairs on page 41.
Installing ISDN BRI hardware
40 ISDN Basic Rate Interface Installation and Commissioning March 2011
To Next Page
Loading...
