Caen V1729 - Correction of the Pedestals; Fig. 2.5: Block Diagram of a Standard Acquisition

PRELIMINARY
Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 3
NPO: Filename: Number of pages: Page:
00109/04:V1729.MUTx/03 V1729_REV3.DOC 38 12
Fig. 2.5: block diagram of a standard acquisition
2.5.1 Correction of the pedestals
The analog memories of the MATACQ chips present by design dispersions of pedestal
from cell to cell which can reach several tens of mV. On the other hand, the pedestal of a
data cell is extremely reproducible (250µV RMS). Due to the structure of the chip, the
dispersion of the pedestals presents a principal periodicity of 20 cells, followed by a tiny
individual distribution. If not compensated, this dispersion will appear as a noise at the
reconstruction of the signal because of the random position of the trigger in the matrix.
Board Parameters Initialization
Send START
A
CQUISITIO
N
Wait for REQUEST
Trigger
auto ?
Send SOFT TRIGGER
yes
no
Read Data:
• Read verniers & samples.
• Read TRIG_REC
Correct & Reorder Data:
• Subtract pedestals.
• Reorder data & calculate times
next acquisition
Send RESET BOARD
Wait for end of PRETRIG