PRELIMINARY
Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 3
NPO: Filename: Number of pages: Page:
00109/04:V1729.MUTx/03 V1729_REV3.DOC 38 15
Where:
dT is the sampling period (500ps or 1ns)
DT0 is a fixed temporal offset, close to 0, due to signal propagation times in the board (of
which the calibration is described in 3.1.1)
An alternative but equivalent solution, consists in generating the reordered table through
a rotation towards the left of the data of :
(1b) ROT = (TRIG_REC - POSTTRIG ) * 20 – INT(Correc_Ver*20) cells
where INT corresponds to rounding off to the nearest whole number.
The trigger is then situated at a time
(5) tT= [Correc_Ver*20– INT(Correc_Ver*20)]* dT
before the cell numbered 20*(128-POSTTRIG) (plus the offset DT0).
To Next Page
Loading...