5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1 = HIGH : Tied to 1.5V~1.854V (Nominal 1.8V)
0 = Low : Tied to 0V~0.3V
M = Middle : Tied to 0.5V~1.3V (Nominal 0.9V)
XTAL
(0x0) Default
Micron MT61K256M32JE-14:A (A-die) 4000MHz 256Mx32
1= SMB_ALT_ADDR Enable
0= SMB_ALT_ADDR Disable
1= DEVID_SEL Rebrand (GSYNC)
0= DEVID_SEL Original (non-GSYNC)
1= PCIE_CFG Low Power
0= PCIE_CFG High Power
1= VGA_DEVICE Enable
0= VGA_DEVICE Disable
Samsung K4Z80325BC-HC14 (C-die) 4000MHz 256Mx32
M
0
M
21 (0x0015)
MM
0 22 (0x0016)
MM
1 23 (0x0017)
M
1
M
24 (0x0018)
1
MM
25 (0x0019)
10
M
16 (0x0010)
1
M
0
17 (0x0011)
1
M
1 18 (0x0012)
11
M
19 (0x0013)
0
MM
20 (0x0014)
01
M 11 (0x000B)
M
00 12 (0x000C)
M
01 13 (0x000D)
M
10
14 (0x000E)
M
1 1 15 (0x000F)
1 1 0 6 (0x0006)
1 1 1 7 (0x0007)
00
M
8 (0x0008)
0
M
0 9 (0x0009)
0
M
1
10 (0x000A)
0 0 1 1 (0x0001)
0 1 0 2 (0x0002)
0 1 1 3 (0x0003)
1 0 0 4 (0x0004)
1 0 1 5 (0x0005)
Strap 2 Strap 1 Strap 0
RAMCFG[4:0]
0 0 0 0 (0x0000)
M M M 26 (0x001A)
(0x0) Default
Strap 5 Strap 4 Strap 3 SMB_ALT_ADDR
0
DEVID_SEL PCIE_CFG
0
VGA_DEVICE
00
0
00
0
0
0
0
0
1
1
11
1
1
0
0
0
1
0
0
1
00
0
0
0
0
00
1
000
110
111
100
010
101
100
101
0
M
1
0
M
0
M
01
01
M
M
00
00
M
1
M
0
M
11 1 1 1
111
11 1
11
111
1
1
1
111
11
1
000
00
00
ROM_SI
ROM_SCLK
ROM_SO
00
00
STRAP[0:2]
Setting RAM type
MULTI-LEVEL STRAPS
Strap5
non-Gsync = L
Gsync = H
Hynix H56C8H24MJR-S2C (M-die) 4000MHz 256Mx32
(0x1)
(0x2)
(0x1)
(0x2)
0
1
Near the GPU
STRAP[0:2]
Setting RAM type
Default
FS_OVERT# Enable
FS_OVERT# Disable
XTALOUT
XTALSSIN
XTALOUTBUFF
XTALIN
1V8_AON
1V8_AON 1V8_AON
1V8_RUN
1V8_RUN[14,15,27,28,69]
1V8_AON[16,17,18,19,21,22,23,24,28,29,30,31,32,67,69,70]
VGA_ROM_SCLK[28]
VGA_ROM_SO[28]
VGA_ROM_SI[28]
STRAP0[28]
STRAP1[28]
STRAP2[28]
STRAP3[28]
STRAP4[28]
STRAP5[28]
GPU_PLLVDD_XS_SP[26,27]
Title
Size Document Number R e v
Date: Sheet
of
6-71-PB5D0-D02
D02
[25] GPU V STRAPS,XTAL
A3
25 84Friday, December 27, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R e v
Date: Sheet
of
6-71-PB5D0-D02
D02
[25] GPU V STRAPS,XTAL
A3
25 84Friday, December 27, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R e v
Date: Sheet
of
6-71-PB5D0-D02
D02
[25] GPU V STRAPS,XTAL
A3
25 84Friday, December 27, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
R174
100K_1%_04
R626
*100K_04
13/22 XTAL/PLL
U3V
N18E
BL6
XTALIN
BJ6
EXT_REFCLK_FL
BB24
XSN_PLLVDD
AF11
GPCPLL_AVDD1
U42
GPCPLL_AVDD0
BC12
VID_PLLVDD
BD12
SP_PLLVDD
BM6
XTALOUT
BK6
XTALOUTBUFF
R164
*100K_04
R631
*100K_04
C358
0.47u_4V_X6S_02
R173
100K_1%_04
R178
100K_04
R622
*100K_04
R172
100K_1%_04
C799
0.47u_4V_X6S_02
R180
*100K_1%_04
R177
*100K_04
X4
U83-076_27MHZ
21
34
R620
100K_04
R176
*100K_04
R611 10K_04
R171
100K_04
OPTION_GPU (W/ GSYNC)
R181
*100K_1%_04
C331
0.47u_4V_X6S_02
R617
100K_04
L33
HCB1608KF-300T60 C655
22u_6.3V_X6S_08
R158
100K_04
OPTION_GPU (W/O GSYNC)
C359
0.47u_4V_X6S_02
R161
100K_04
C618
0.47u_4V_X6S_02
C769
4.7u_6.3V_X6S_06
R621
100K_04
C1344
12p_50V_NPO_04
R170
10K_04
R182
*100K_1%_04
C1346
12p_50V_NPO_04
To Next Page
Loading...
