5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPI_BIOS ROM 128MB
SPI_* = 1"~6.5"
炻
Zo= 50Ω
128Mbit / 3.3V
MXIC P/N = 6-04-25128-A72
Pin Straps(2)
RESERVED
External pull-up is required.
Recommend 100K if pulled up
to 3.3V or 75K if pulled up
to 1.8V.
This strap should sample
HIGH. There should NOT be
any on-board device driving
it to opposite direction
during strap sampling.
ESPI FLASH SHARING MODE
HIGH=SLAVE ATTACEHD FLASH SHARING (SAFS)
LOW=MASTER ATTACHED FLASH SHARING (MAFS)
(INTERNAL WEAK PD)
CONSENT STRAP
LOW=ENABLE
PESONALITY STRAP
ENABLE:LOW
BOOT HALT
LOW=ENABLE
(INTERNAL WEAK PU)
JTAG ODT
LOW=DISABLE
(INTERNAL WEAK PU)
VCCPSPI VOLTAGE SELECT
HIGH=1.8V
LOW=3.3V (DEFAULT)
(INTERNAL WEAK PD)
close to PCH
DIFF=85ohm, L<3"~10"
To M.2
Zo=50ohm, L<10"
To M.2
W/O TPM
W/ TPM
W/O TPM
W/ TPM
close to PCH
GPP_J4
XTAL FREQUENCY SELECT
HIGH=24MHz XTAL frequency selected.
LOW=38.4 XTAL frequency selected. (Default; Not supported)
20191106 Add R861 75K_04_Intel V3.0 Update
20191125 Change to GPP_B3
DDS_DET
HIGH=W/ DDS PANEL
LOW=W/O DDS PANEL
GSYNC_DET
HIGH=W/ GSYNC PANEL
LOW=W/O GSYNC PANEL
W/ TPM
R354,R349.R387=5.1_1%_04
W/O TPM
R354,R349,R387=22_04
W/ TPM
R851,R844,R845=56_1%_04
W/O TPM
R851,R844,R845=22_04
20191230 Follow common
20191230 Follow common
SPI_SI_M
SPI_SO_M
SPI_SCLK_M
SPI_CS_0#SPI_WP# SPI_CS0#
SPI_HOLD#
GPP_H12
GPP_H15
SPI_WP#
SPI_HOLD#
TBTA_MRESET
GPP_H15
GPP_H12
SPI_IO2
SPI_IO3
SPI_SI_R
SPI_SO_R
SPI_IO3
SPI_IO2
GPP_A11
GSYNC_DET
GPP_G1
DDS_DET
GPPJ_RCOMP_1P8
SD_RCOMP_3P3
SD_RCOMP_1P8
PCIECOMP_N
PCIECOMP_P
GPP_J1
CNVI_MFUART2_TXD
CNVI_BRI_DT_R
CNVI_RGI_DT_R
GSYNC_DET
CNVI_MFUART2_TXD
CNVI_RGI_RSP
CNVI_BRI_RSP
SPI_SI_R
SPI_CS_0#
SPI_SCLK_R
SPI_SO_R
GPP_J1
DDS_DET
SPI_SO_R
SPI_SI_R
SPI_SCLK_R
VCC_RTC
SPI_3.3V
3.3VA
3.3VA
SPI_3.3V
SPI_3.3V
3.3VS
VCCPRIM_1P8
VCCPRIM_1P8
VDD3
3.3VA
VCCPRIM_1P8
3.3VS[8,9,10,11,12,28,32,35,36,37,38,41,42,43,44,45,47,49,54,56,57,58,59,63,64,70]
3.3VA[4,32,35,36,39,41,43,59,61,62,63]
VCC_RTC[36,39]
PLT_RST# [32,41]
TBT_RTD3_PWR_EN_R [46]
TBTA_HRESET [48]
TBT_FORCE_PWR_R [46]
GPP_K12_PLVDD_SEL [10]
GPP_J1[63]
CNVI_BRI_DT[55]
CNVI_RGI_DT[55]
CNVI_RGI_RSP[55]
CNVI_BRI_RSP[55]
CNVI_GNSS_PA_BLANKING[55]
CNVI_MFUART2_RXD[55]
CNVI_MFUART2_TXD[55]
CNVI_WT_D1N [55]
CNVI_WT_D1P [55]
CNVI_WR_D0N [55]
CNVI_WR_D0P [55]
CNVI_WR_D1N [55]
CNVI_WR_D1P [55]
CNVI_WR_CLKN [55]
CNVI_WR_CLKP [55]
CNVI_WT_CLKN [55]
CNVI_WT_CLKP [55]
CNVI_WT_D0N [55]
CNVI_WT_D0P [55]
SWI#_GPP_G6[35]
SATA_PWR_EN[56]
GPP_K15_INTP_OUT [52]
GPP_K14_TEST_R [52]
SPI_CS_2#[43]
VCCPRIM_1P8[39,55]
EC_SPI_CS_0# [42]
EC_SPI_SCLK_R [42]
EC_SPI_SO_R [42]
EC_SPI_SI_R [42]
SPI_3.3V[39]
VDD3[4,10,28,32,34,35,36,39,41,42,45,54,55,56,57,59,60,61,62,63,64,65,67,69,70,71]
TPM_SPI_SCLK_R [43]
TPM_SPI_SO_R [43]
TPM_SPI_SI_R [43]
BT_EN [55]
Title
Size Document Number R ev
Date: Sheet
of
6-71-PB5D0-D02
D02
[33] PCH A,M SPI/SMB/CN
A3
33 84Thursday, January 16, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R ev
Date: Sheet
of
6-71-PB5D0-D02
D02
[33] PCH A,M SPI/SMB/CN
A3
33 84Thursday, January 16, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R ev
Date: Sheet
of
6-71-PB5D0-D02
D02
[33] PCH A,M SPI/SMB/CN
A3
33 84Thursday, January 16, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
R449 0_04
R266 10K_04 OPTION_W/O GSYNC
C1550
0.1u_6.3V_X5R_02
R411 0_04
R405
33_04
R846 0_04
R447 0_04
R246 200_1%_04
R350 *4.7K_04
T96
R720 100_1%_04
R410 100K_04
R419 *20K_04
R689 100K_04 W/ DDS
R825 *1K_04
R369 *100K_04
R346 1M_04
R257 100K_04 OPTION_W/ GSYNC
13 OF 13
U30M
CML-H QS64
CNV_WR_CLKN
BD4
CNV_WR_CLKP
BE3
CNV_WR_D0N
BB3
CNV_WR_D0P
BB4
CNV_WR_D1N
BA3
CNV_WR_D1P
BA2
CNV_WT_CLKN
BC5
CNV_WT_CLKP
BB6
CNV_WT_D0N
BE6
CNV_WT_D0P
BD7
CNV_WT_D1N
BG6
CNV_WT_D1P
BF6
CNV_WT_RCOMP
BA1
GPPJ_RCOMP_1P81
BD1
GPPJ_RCOMP_1P82
BE1
GPP_J0/CNV_PA_BLANKING
AV6
GPP_I11/M2_SKT2_CFG0
AP3
GPP_G7/SD_WP
AV13
GPP_G5/SD_CD#
BE8
GPP_I12/M2_SKT2_CFG1
AP2
PCIE_RCOMPN
B12
GPP_J9/CNV_MFUART2_TXD
AU9
GPP_I13/M2_SKT2_CFG2
AN4
GPP_I14/M2_SKT2_CFG3
AM7
PCIE_RCOMPP
A13
GPP_G6/SD_CLK
BD8
GPP_J8/CNV_MFUART2_RXD
AW2
GPP_J10
AV7
TP
AL35
RSVD2
Y35
GPP_J11/A4WP_PRESENT
AR13
RSVD1
BC1
GPP_J2
AW3
GPP_G4/SD_DATA3
BG8
GPP_J3
AT10
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
AV3
GPP_J1/CPU_C10_GATE#
AY3
GPP_J4/CNV_BRI_DT/UART0B_RTS#
AV4
SD_1P8_RCOMP
BE5
GPP_J5/CNV_BRI_RSP/UART0B_RXD
AY2
GPP_J6/CNV_RGI_DT/UART0B_TXD
BA4
SD_3P3_RCOMP
BE4
GPP_G3/SD_DATA2
BF9
GPPJ_RCOMP_1P83
BE2
GPP_G2/SD_DATA1
BF8
RSVD3
Y36
GPP_G0/SD_CMD
AW13
GPP_G1/SD_DATA0
BE9
R403 *20K_04
R692 200_1%_04
R841 0_04
R236 10K_04
R241 200_1%_04
R406 33_04
T105
R237 20K_04
R240 33_04
R349 5.1_1%_04
R389 *20K_04
R359 *4.7K_04
R842
20K_04
R826 *4.7K_04
R843 0_04
R354 5.1_1%_04
R851 56_1%_04
R388 *20K_04
R844 56_1%_04
R387 5.1_1%_04
U60
MX25L12872FM2I-10G
CE#
1
SO
2
WP#
3
VSS
4
SI
5
SCK
6
HOLD#
7
VDD
8
R220 20K_04
1 OF 13
U30A
CML-H QS64
SPI0_CLK
AW47
GPP_D22/SPI1_IO3
BC17
SPI0_MISO
BA45
SPI0_MOSI
AU41
GPP_K14/GSXDIN
W46
GPP_E3/CPU_GP0
AL47
GPP_H16/SML4CLK
AE43
GPP_B4/CPU_GP3
BC33
GPP_K16/GSXCLK
Y47
GPP_B3/CPU_GP2
BF32
GPP_E7/CPU_GP1
AM45
GPP_H17/SML4DATA
AJ46
SPI0_IO2
AY48
GPP_B13/PLTRST#
AV29
GPP_H14/SML3DATA
AD48
SPI0_IO3
BA46
SPI0_CS2#
AT40
GPP_H10/SML2CLK
AE48
GPP_H11/SML2DATA
AD47
SPI0_CS1#
AW48
GPP_K12/GSXDOUT
Y46
GPP_D21/SPI1_IO2
BD17
SPI0_CS0#
AY47
GPP_H18/SML4ALERT#
AE44
TP
AN35
GPP_H15/SML3ALERT#
AC47
GPP_K15/GSXSRESET#
AA45
GPP_K13/GSXSLOAD
Y48
RSVD1
R13
GPP_H13/SML3CLK
AF47
GPP_H12/SML2ALERT#
AB47
INTRUDER#
BB44
GPP_D0/SPI1_CS#/SBK0/BK0
BF19
GPP_D1/SPI1_CLK/SBK1/BK1
BE19
GPP_D3/SPI1_MOSI/SBK3/BK3
BF18
VSS_AL37
AL37
GPP_D2/SPI1_MISO/SBK2/BK2
BE18
RSVD2
R15
GPP_A11/PME#/SD_VDD2_PWR_EN#
BE36
R849
20K_04
R840 0_04
R448 0_04
R404 0_04
R221 33_04
R845 56_1%_04
R683 150_1%_04
R685 10K_04 W/O DDS
R861 75K_04
R852 0_04
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