Clevo PB70DDS - Power Sequence

Schematic Diagrams
B - 86 Power Sequence
B.Schematic Diagrams
Power Sequence
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VA_E C_ EN
5V
SUSB#
VDDQ=VCCSFR_OC
VCORE
H_PWRGD
DDR4_DRAMRST#
PLT_RST#
2.5V
DDR_VTT_PG_CTRL
20ms
100ms
AC_IN
0ms
427.68us
PWR_BTN#
width
105.86ms
SUSC#
VDDQ_PG_R
3.22ms
( rise :1.15ms )
1.11ms
( rise :1.18ms )
5.29ms
SUSC# to SUSB#: 33.43us
3.3VS
6.54ms
5VS
564.03us
( rise :517.17us )
818.02us
( rise :1ms )
VCCIO_PWRGD=ALL_SYS_PWRGD
7.84ms
VCORE_PG
PM_PWROK
SYS_PWROK
167.49ms
230.65ms
232.13ms
310.30ms
6.53ms
VCCST_PWRGD
VCCST_PWRGD to DDR_VTT_PG_CNTL: 42ns
VTT_MEM
235.25ms
1.05VA
3.3VA
243.96us
( rise :101.62us )
949.03us
( rise :355.98us )
3.3V
431.52us
SUSBC_EN#
8.49us
( rise :418.67us )
L: 179.94ms; H: 330.90ms
1.05V_VCCST=1.05V_VCCSFR
6.52us
6.59ms
166.34ms
911.79ms
DD_ON
30.00ms
( rise :501.75us )
RSMRST#
79.99ms
1.05V_VCCSTG
12.26us
VCCIO
764.56us
( rise :513.39us )
VCCSA
2.60ms
( rise :37.87us )
( rise :29us )
VDD5
1.83ms
SLP_SUS_EC# to DD_ON
( rise :2.52ms )
SLP_SUS_EC# to RSMRST#
SLP_SUS_EC# to SUSC#
VCCPRIM_1P8
230.05us
( rise :55.41us )
VCCPRIM_1P8 = PCH Internal voltage, test R274
Title
Size Document Number R ev
Date: Sheet
of
6-77-PB70DF2-D02-C
D02
[85] SEQUENCE
A3
85 85Monday, December 30, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R ev
Date: Sheet
of
6-77-PB70DF2-D02-C
D02
[85] SEQUENCE
A3
85 85Monday, December 30, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R ev
Date: Sheet
of
6-77-PB70DF2-D02-C
D02
[85] SEQUENCE
A3
85 85Monday, December 30, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Sheet 85 of 85
Power Sequence